Read Compensation Circuits and Apparatus Using Same

• US 20100103737A1
• Filed: 10/02/2009
• Published: 04/29/2010
• Est. Priority Date: 10/28/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Ki Tae
• Granted Patent: US 8,243,515 B2
• Time in Patent Office: Days
• US Class Current: 365/185.90
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

A read compensation circuit is provided. The read compensation circuit corrects a read error occurring in an erased cell based on a pattern of programmed cells adjacent to the erased cell. The read compensation circuit also transmit program state information of a memory cell stored in a page buffer to another page buffer through a bit line, thereby allowing page buffers to easily detect and correct errors occurring in memory cells.

Claims

1. A read compensation circuit comprising:

a plurality of memory cells comprising at least one erased cell; and

a correction circuit that is configured to correct an error in the erased cell based on program state information of cells adjacent the erased cell.

2. The read compensation circuit of claim 1, wherein the correction circuit comprises a plurality of page buffers respectively connected with the plurality of memory cells and each of the page buffers stores the program state information of a memory cell connected with each page buffer among the plurality of memory cells and sends the program state information to other page buffers among the plurality of page buffers.

3. The read compensation circuit of claim 2, wherein the plurality of page buffers are divided into a first page buffer block and a second page buffer block separated from the first page buffer block by the plurality of memory cells,

wherein one of the first and second page buffer blocks sends the program state information to an other of the first and second page buffer blocks through a bit line.

4. The read compensation circuit of claim 2, further comprising a control logic that is configured to output a control signal for correcting the program state information stored in the plurality of page buffers, wherein at least one of the plurality of page buffers corrects the program state information in response to the control signal.

5. The read compensation circuit of claim 4, wherein the at least one of the plurality of page buffers corrects the program state information of the erased cell whose total threshold voltage shift exceeds a predetermined value in response to the control signal.

6. The read compensation circuit of claim 5, wherein the total threshold voltage shift is determined based on at least one between program disturbance and coupling occurring due to the cells adjacent the erased cell.

7. The read compensation circuit of claim 4, wherein the plurality of page buffers perform a read operation using a first level as a reference and determine the program state information of the respective memory cells and the at least one of the plurality of page buffers performs a read operation using a second level greater than the first level in response to the control signal to correct the program state information of the erased cell.

8. The read compensation circuit of claim 1, wherein the correction circuit is a controller that is configured to receive the program state information from each of the memory cells and to check whether error correcting code (ECC) correction has been successful.

9. The read compensation circuit of claim 8, wherein the controller comprises a read engine that is configured to correct the error in the erased cell based on the program state information of the cells adjacent the erased cell and, when the ECC correction has failed, the controller performs mapping conversion to convert the program state information received from the plurality of memory cells into physical data and input the physical data to the read engine.

10. The read compensation circuit of claim 9, wherein the read engine corrects the program state information of the erased cell whose total threshold voltage shift exceeds a predetermined value based on the physical data.

11. A read compensation circuit comprising:

a plurality of memory cells comprising at least one erased cell;

a correction circuit that is configured to correct an error in the erased cell based on program state information of cells adjacent the erased cell, the correction circuit comprising a plurality of page buffers that are connected to respective ones of the plurality of memory cells; and

a control logic that is configured to output a control signal for correcting the program state information stored in the plurality of page buffers, wherein at least one of the plurality of page buffers corrects the program state information in response to the control signal.

12. The read compensation circuit of claim 11, wherein each of the page buffers stores the program state information of a memory cell connected with each page buffer among the plurality of memory cells and sends the program state information to other page buffers among the plurality of page buffers.

13. The read compensation circuit of claim 12, wherein the plurality of page buffers are divided into a first page buffer block and a second page buffer block separated from the first page buffer block by the plurality of memory cells, and

wherein one of the first and second page buffer blocks sends the program state information to an other of the first and second page buffer blocks through a bit line.

14. The read compensation circuit of claim 12, wherein the at least one of the plurality of page buffers corrects the program state information of the erased cell whose total threshold voltage shift exceeds a predetermined value in response to the control signal.

15. The read compensation circuit of claim 14, wherein the total threshold voltage shift is determined based on at least one between program disturbance and coupling occurring due to the cells adjacent the erased cell.

16. The read compensation circuit of claim 12, wherein the plurality of page buffers perform a read operation using a first level as a reference and determine the program state information of the respective memory cells and the at least one of the plurality of page buffers performs a read operation using a second level greater than the first level in response to the control signal to correct the program state information of the erased cell.

17. The read compensation circuit of claim 11, wherein the correction circuit comprises a controller that is configured to receive the program state information from each of the memory cells and to check whether error correcting code (ECC) correction has been successful.

18. The read compensation circuit of claim 17, wherein the controller comprises a read engine that is configured to correct the error in the erased cell based on the program state information of the cells adjacent the erased cell and, when the ECC correction has failed, the controller performs mapping conversion to convert the program state information received from the plurality of memory cells into physical data and input the physical data to the read engine.

19. The read compensation circuit of claim 18, wherein the read engine corrects the program state information of the erased cell whose total threshold voltage shift exceeds a predetermined value based on the physical data.

20. A memory storage apparatus that includes a read compensation circuit according to claim 11.