REAL-TIME NETWORK VIDEO PROCESSING

• US 20100104006A1
• Filed: 10/28/2008
• Published: 04/29/2010
• Est. Priority Date: 10/28/2008
• Status: Abandoned Application

• Current Assignee: Panzura, Inc.
• Original Assignee: Pixel8 Networks, Inc. (Panzura, Inc.)
• Inventors: Adam, Joel Frederic, Taylor, John Richard, Chou, Randy Yen-pang
• Application Number:
  US12/260,032
• Publication Number:
  US 20100104006A1
• Time in Patent Office: Days
• US Class Current: 375/240.200
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

An embodiment is a method and apparatus to process video frames. An entropy decoder performs entropy decoding on a bitstream of a video frame extracted from a network frame. The entropy decoder generates discrete cosine transform (DCT) coefficients representing a picture block in the video frame. The entropy decoder is configured for serial operations. A graphics processing unit (GPU) performs image decoding using the DCT coefficients. The GPU is configured for parallel operations.

One disclosed feature of the embodiments is a technique to decode a video frame. A GPU performs image encoding of a video frame computing quantized DCT coefficients representing a picture block in the video frame. The GPU is configured for parallel operations. An entropy encoder performs entropy encoding on the quantized DCT coefficients. The entropy encoder is configured for serial operations.

Claims

1. An apparatus comprising:

an entropy decoder to perform entropy decoding on a bitstream of a video frame extracted from a network frame, the entropy decoder generating discrete cosine transform (DCT) coefficients representing a picture block in the video frame, the entropy decoder being configured for serial operations; and

a graphics processing unit (GPU) coupled to the entropy decoder to perform image decoding using the DCT coefficients, the GPU being configured for parallel operations.

2. The apparatus of claim 1 wherein the entropy decoder comprises a variable length decoder to perform a variable length decoding on the bitstream.

3. The apparatus of claim 2 wherein the entropy decoder further comprises a run length decoder to perform a run length decoding on the bitstream.

4. The apparatus of claim 1 wherein the entropy decoder is implemented using a field programmable gate array (FPGA).

5. The apparatus of claim 4 wherein the entropy decoder comprises an arithmetic coding (AC) decoder to perform an AC decoding on the bitstream.

6. The apparatus of claim 1 wherein the entropy decoding is compatible with at least one of an MPEG-2 standard and an H.264 standard.

7. The apparatus of claim 1 wherein the GPU performs at least one of an inverse quantization, an inverse DCT, a video reconstruction, a filtering, and an inter- or intra-frame prediction.

8. The apparatus of claim 1 wherein the image decoding is compatible with at least one of an MPEG-2 standard and an H.264 standard.

9. The apparatus of claim 1 wherein the network frame is an Ethernet frame.

10. The apparatus of claim 1 further comprising:

a network interface unit to receive the network frame from a data server via a network; and

a network processor coupled to the network interface unit to extract the video frame from the network frame.

11. The apparatus of claim 10 wherein the network processor comprises:

a video detector to detect the video frame in the network frame; and

a video parser coupled to the video detector to parse the network frame into the video frame.

12. An apparatus comprising:

a graphics processing unit (GPU) to perform image encoding of a video frame computing quantized discrete cosine transform (DCT) coefficients representing a picture block in the video frame, the GPU being configured for parallel operations; and

an entropy encoder coupled to GPU to perform entropy encoding on the quantized DCT coefficients, the entropy encoder being configured for serial operations.

13. The apparatus of claim 12 wherein the entropy encoder comprises a variable length encoder to perform a variable length encoding on the quantized DCT coefficients.

14. The apparatus of claim 13 wherein the entropy encoder further comprises a run length encoder to perform a run length encoding on the quantized DCT coefficients.

15. The apparatus of claim 12 wherein the entropy encoder is implemented using a field programmable gate array (FPGA).

16. The apparatus of claim 15 wherein the entropy encoder comprises an arithmetic coding (AC) encoder to perform an AC encoding on the quantized DCT coefficients.

17. The apparatus of claim 12 wherein the entropy encoding is compatible with at least one of an MPEG-2 standard and an H.264 standard.

18. The apparatus of claim 12 wherein the GPU performs at least one of an residual computation, a DCT, a quantization on the DCT coefficients, and a decoding.

19. The apparatus of claim 12 wherein the image encoding is compatible with at least one of an MPEG-2 standard and an H.264 standard.

20. The apparatus of claim 12 further comprising:

a network processor coupled to the entropy encoder to encapsulate the encoded video frame into a network frame; and

a network interface unit to transmit the network frame to a client via a network.

21. The apparatus of claim 20 wherein the network frame is an Ethernet frame.

22. A method comprising:

performing entropy decoding, on a serial processing device, on a bitstream of a video frame extracted from a network frame to generate discrete cosine transform (DCT) coefficients representing a picture block in the video frame; and

performing image decoding of the video frame using the DCT coefficients on a parallel processing device.

23. The method of claim 22 wherein performing entropy decoding comprises performing at least one of a variable length decoding, a run length decoding, and an arithmetic coding (AC) decoding on the bitstream.

24. The method of claim 22 further comprising:

receiving the network frame from a data server via a network; and

extracting the video frame from the network frame.

25. The method of claim 24 wherein extracting the video frame comprises:

detecting the video frame in the network frame; and

parsing the network frame into the video frame.

26. The method of claim 22 wherein the serial processing device is a field programmable gate array (FPGA).

27. The method of claim 22 wherein the entropy decoding is compatible with at least one of an MPEG-2 standard and an H.264 standard.

28. A method comprising:

performing image encoding of a video frame on a parallel processor computing quantized discrete cosine transform (DCT) coefficients representing a picture block in the video frame; and

performing entropy encoding of the quantized DCT coefficients on a serial processing device.

29. The method of claim 28 wherein performing entropy encoding comprises performing at least one of a variable length encoding, a run length encoding, and an arithmetic coding (AC) encoding on the quantized DCT coefficients.

30. The method of claim 29 further comprising:

encapsulating the encoded video frame into a network frame; and

transmitting the network frame to a client via a network.

31. The method of claim 28 wherein the serial processing device is a field programmable gate array (FPGA).

32. The method of claim 28 wherein the entropy decoding is compatible with at least one of an MPEG-2 standard and an H.264 standard.