MULTILEVEL-CELL MEMORY STRUCTURES EMPLOYING MULTI-MEMORY LAYERS WITH TUNGSTEN OXIDES AND MANUFACTURING METHOD

• US 20100105165A1
• Filed: 01/06/2010
• Published: 04/29/2010
• Est. Priority Date: 01/19/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: HO, ChiaHua, Lai, Erh-Kun
• Granted Patent: US 8,597,976 B2
• Time in Patent Office: Days
• US Class Current: 438/104
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

Claims

1. A method for manufacturing a memory device, comprising:

forming a first electrode comprising a metal material, the first electrode extending to a top surface of a dielectric layer;

etching the first electrode to remove a portion of the first electrode, thereby forming a recess extending below the top surface of the dielectric layer;

forming a dielectric sidewall spacer within the recess and on the first electrode, the dielectric sidewall spacer having an inner surface defining an opening within the recess, the opening overlying an exposed portion of the first electrode;

oxidizing the exposed portion of the first electrode to form a metal oxide memory element comprising an oxide of said metal material embedded within the first electrode; and

forming a second electrode in contact with the metal oxide memory element.

2. The method of claim 1, wherein forming the second electrode comprises forming a bit line which includes the second electrode.

3. The method of claim 1, wherein:

forming the first electrode comprises;

forming a via within the dielectric layer;

forming a barrier material on sidewalls of the via;

forming the metal material on the barrier material and filling the via; and

etching the first electrode comprises;

etching the metal material using a first etch chemistry; and

etching the barrier material using a second etch chemistry.

4. The method of claim 3, wherein:

the first etch chemistry comprises a SF₆ dry etch; and

the second etch chemistry comprises an etch using chlorine, trichloroborane or argon.

5. The method of claim 1, wherein said oxidizing comprises plasma oxidation.

6. The method of claim 1, further comprising:

forming a first diode, the first diode underlying and electrically coupled to the first electrode;

forming a second diode overlying and electrically coupled to the second electrode; and

forming a second metal oxide memory element, comprising;

forming a third electrode overlying and electrically coupled to the second diode, and extending to a top surface of a second dielectric layer, the third electrode comprising a second metal material;

etching the third electrode to remove a portion of the third electrode, thereby forming a second recess extending below the top surface of the second dielectric layer;

forming a second dielectric sidewall spacer within the second recess and on the third electrode, the second dielectric sidewall spacer having an inner surface defining a second opening within the second recess, the second opening overlying an exposed portion of the third electrode;

oxidizing the exposed portion of the third electrode to form the second metal oxide memory element comprising an oxide of said second metal material and embedded within the third electrode; and

forming a fourth electrode in contact with the second metal oxide memory element.

7. The method of claim 6, further comprising forming a first bit line underlying and electrically coupled to the first diode, and wherein:

forming the second electrode comprises forming a second bit line which includes the second electrode; and

forming the fourth electrode comprising forming a third bit line which includes the fourth electrode.

8. The method of claim 7, wherein:

the first bit line and the second bit line are arranged in non-parallel directions, and said metal oxide memory element lies in a cross-point between the first and second bit lines; and

the second bit line and the third bit line are arranged in non-parallel directions, and the second metal oxide memory element lies in a cross-point between the second and third bit lines.

9. A method for manufacturing a memory device, comprising:

forming a first electrode;

forming a metal oxide memory element electrically coupled to the first electrode; and

forming a second electrode electrically coupled to the metal oxide memory element, wherein the metal oxide memory element has a width transverse to an inter-electrode current path between the first and second electrodes through the metal oxide memory element which is less than a width of the first electrode.

10. The method of claim 9, further comprising:

forming a third electrode electrically coupled to the second electrode;

forming a second metal oxide memory element electrically coupled to the third electrode; and

forming a fourth electrode electrically coupled to the second metal oxide memory element, wherein the second metal oxide memory element has a width transverse to an inter-electrode current path between the third and fourth electrodes through the second metal oxide memory element which is less than a width of the third electrode.

11. A method for manufacturing a memory device, comprising:

forming a diode;

forming a metal oxide memory element overlying and electrically coupled to the diode; and

forming an electrode overlying and electrically coupled to the metal oxide memory element, wherein the metal oxide memory element has a width transverse to an inter-electrode current path between the diode and the electrode and through the metal oxide memory element which is less than a width of the diode.

12. The method of claim 11, further comprising:

forming a second diode overlying and electrically coupled to said electrode;

forming a second metal oxide memory element overlying and electrically coupled to the second diode; and

forming a second electrode overlying and electrically coupled to the second metal oxide memory element, wherein the second metal oxide memory element has a width transverse to an inter-electrode current path between the second diode and the second electrode and through the metal oxide memory element which is less than a width of the second diode.