METHOD AND APPARATUS FOR ENFORCING A FLASH MEMORY CACHING POLICY

• US 20100106890A1
• Filed: 10/29/2008
• Published: 04/29/2010
• Est. Priority Date: 10/29/2008
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Afriat, Izhak, Lieber, Opher, LASSER, Menahem
• Granted Patent: US 8,407,399 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die.

Claims

1. ) A flash memory device comprising:

a) a flash memory including a plurality of flash memory dies, each flash memory die including a respective cache storage area and a respective main storage area; and

b) control circuitry operative to;

i) receive data from an external host device;

ii) determine to which main storage area the received data is addressed, thereby specifying one of the plurality of flash memory dies as a target die for the received data; and

iii) whenever the received data is written into a cache storage area before being written into a main storage area, write the received data into the cache storage area of the specified target die.

2. ) The device of claim 1 wherein the control circuitry is operative such that all data received from the external host device is written into a cache storage area before being written into a main storage area.

3. ) The device of claim 1 wherein the control circuitry is operative such that some data received from the external host device is written into a cache storage area before being written into a main storage area, while other data received from the external host device is written into a main storage area without first being written into a cache storage area.

4. ) The flash memory device of claim 1 wherein the control circuitry is operative, whenever the received data is written into a cache storage area before being written into a main storage area, to write the received data into only one cache storage area.

5. ) The flash memory device of claim 1 wherein the control circuitry is operative to determine to which main storage area the received data is addressed in accordance with address information for the received data that is received from the external host device.

6. ) The flash memory device of claim 1 wherein for each die of the plurality of flash memory dies, the respective main storage area is configured to store more bits per flash cell than the respective cache storage area.

7. ) The flash memory device of claim 1 wherein the control circuitry is further operative to locally copy the received data from the cache storage area of the specified target die to the main storage area of the specified target die such that the data does not leave the target storage die during the local copying.

8. ) The flash memory device of claim 7 wherein:

i) for each die of the plurality of dies, the control circuitry is operative to carry out a respective local copying; and

ii) the control circuitry is operative to simultaneously carry out the local copyings for the different dies of the plurality of dies.

9. ) The flash memory device of claim 1 wherein the control circuitry includes at least one of software and firmware.

10. ) The flash memory device of claim 1 wherein:

A) each die of the plurality of dies includes a respective plurality of planes, each plane including a respective plane cache storage area and a respective plane main storage area; and

B) the control circuitry is further operative to;

iv) determine to which plane main storage area on the target die the received data is addressed, thereby specifying one of the planes of the target die as a target plane for the received data; and

v) whenever the received data is written into a plane cache storage area before being written into a plane main storage area, write the received data into the plane cache storage area of the specified target plane on the specified target die.

11. ) A method of data caching in a system including a flash memory device coupled to an external host device, the flash memory device including a plurality of flash memory dies, each flash memory die including a respective cache storage area and a respective main storage area, the method comprising:

a) receiving data by the flash memory device from an external host device;

b) determining to which main storage area the received data is addressed, thereby specifying one of the plurality of flash memory dies as a target die for the received data; and

c) whenever the received data is written into a cache storage area before being written into a main storage area, writing the received data into the cache storage area of the specified target die.

12. ) The-method of claim 11 further comprising:

d) whenever the received data is written into a main storage area, writing the received data into the corresponding cache storage area before the data is written into the main storage area.

13. ) The method of claim 11 further comprising:

d) writing a first portion of the received data into the cache storage area of the specified target die; and

e) writing a second portion of the received data into the main storage area of the specified target die without first writing the second portion into any cache storage area.

14. ) The method of claim 11 further comprising:

d) whenever the received data is written into a cache storage area before being written into a main storage area, writing the received data into only one cache storage area

15. ) The method of claim 11 wherein the determining of step (b) is carried out in accordance with address information for the received data that is received from the external host device.

16. ) The method of claim 11 further comprising:

d) whenever the received data is written into a cache storage area before being written into a main storage area;

i) writing the received data into the cache storage area of the specified target die using a first writing mode that provides a first number of bits per flash cell; and

ii) subsequently writing the received data into the main storage area of the specified target die using a second writing mode that provides a second number of bits per flash cell that exceeds the first number.

17. ) The method of claim 11 further comprising:

d) whenever the received data is written into a cache storage area before being written into a main storage area, locally copying the data from the cache storage area of the specified target die to the main storage area of the specified target die such that the data does not leave the target storage die during the local copying.

18. ) The method of claim 17 wherein:

i) a respective local copying is carried out for each die of the plurality of dies; and

ii) the local copyings are simultaneously carried out for the different dies of the plurality of dies.

19. ) The method of claim 11 wherein:

i) the method is performed in a system where each die of the plurality of dies includes a respective plurality of planes, each plane including a respective plane cache storage area and a respective plane main storage area; and

ii) the method further comprises;

d) determining to which plane main storage area on the target die the received data is addressed, thereby specifying one of the planes of the target die as a target plane for the received data; and

e) whenever the received data is written into a plane cache storage area before being written into a plane main storage area, writing the received data into the plane cache storage area of the specified target plane on the specified target die.

20. ) A flash memory device comprising:

a) a flash memory including at least one flash memory die, the flash memory die including a plurality of planes, each plane including a respective cache storage area and a respective main storage area; and

b) control circuitry operative to;

i) receive data from an external host device;

ii) determine to which main storage area the received data is addressed, thereby specifying one of the plurality of flash memory planes as a target plane for the received data; and

iii) whenever the received data is written into a cache storage area before being written into a main storage area, write the received data into the cache storage area of the specified target plane.

21. ) The flash memory device of claim 20 wherein the control circuitry is operative such that all data received from the external host device is written into a cache storage area before being written into a main storage area.

22. ) The flash memory device of claim 20 wherein the control circuitry is operative such that some data received from the external host device is written into a cache storage area before being written into a main storage area, while other data received from the external host device is written into a main storage area without first being written into a cache storage area.

23. ) The flash memory device of claim 20 wherein the control circuitry is operative, whenever the received data is written into a cache storage area before being written into a main storage area, to write the received data into only one cache storage area.

24. ) The flash memory device of claim 20 wherein the control circuitry is operative to determine to which main storage area the received data is addressed in accordance with address information for the received data that is received from the external host device.

25. ) The flash memory device of claim 20 wherein for each plane of the plurality of flash memory planes, the respective main storage area is configured to store more bits per flash cell than the respective cache storage area.

26. ) The flash memory device of claim 20 wherein the control circuitry is further operative to locally copy the received data from the cache storage area of the specified target plane to the main storage area of the specified target plane such that the data does not leave the target storage plane during the local copying.

27. ) The flash memory device of claim 26 wherein:

i) for each plane of the plurality of planes, the control circuitry is operative to carry out a respective local copying; and

ii) the control circuitry is operative to simultaneously carry out the local copying for the different planes of the plurality of planes.

28. ) The flash memory device of claim 20 wherein the control circuitry includes at least one of software and firmware.

29. ) A method of data caching in a system including a flash memory device coupled to an external host device, the flash memory device including at least one flash memory die, the flash memory die including a plurality of planes, each plane including a respective cache storage area and a respective main storage area, the method comprising:

a) receiving data by the flash memory device from an external host device;

b) determining to which main storage area the received data is addressed, thereby specifying one of the plurality of flash memory planes as a target plane for the received data; and

c) whenever the received data is written into a cache storage area before being written into a main storage area, writing the received data into the cache storage area of the specified target plane.

30. ) The method of claim 29 further comprising:

d) whenever the received data is written into a main storage area, writing the received data into the corresponding cache storage area before the data is written into the main storage area.

31. ) The method of claim 29 further comprising:

d) writing a first portion of the received data into the cache storage area of the specified target plane; and

e) writing a second portion of the received data into the main storage area of the specified target plane without first writing the second portion into any cache storage area.

32. ) The method of claim 29 further comprising:

d) whenever the received data is written into a cache storage area before being written into a main storage area, writing the received data into only one cache storage area

33. ) The method of claim 29 wherein the determining of step (b) is carried out in accordance with address information for the received data that is received from the external host device.

34. ) The method of claim 29 further comprising:

d) whenever the received data is written into a cache storage area before being written into a main storage area;

i) writing the received data into the cache storage area of the specified target plane using a first writing mode that provides a first number of bits per flash cell; and

ii) subsequently writing the received data into the main storage area of the specified target plane using a second writing mode that provides a second number of bits per flash cell that exceeds the first number.

35. ) The method of claim 29 farther comprising:

d) whenever the received data is written into a cache storage area before being written into a main storage area, locally copying the data from the cache storage area of the specified target plane to the main storage area of the specified target plane such that the data does not leave the target storage plane during the local copying.

36. ) The method of claim 35 wherein:

i) a respective local copying is carried out for each plane of the plurality of planes; and

ii) the local copyings are simultaneously carried out for the different planes of the plurality of planes.

37. ) A computer readable medium having stored therein computer readable program code for data caching in a system including a flash memory device coupled to an external host device, the flash memory device including a plurality of flash memory dies, each flash memory die including a respective cache storage area and a respective main storage area, the program code being operable to:

a) receive data by the flash memory device from an external host device;

b) determine to which main storage area the received data is addressed, thereby specifying one of the plurality of flash memory dies as a target die for the received data; and

c) whenever the received data is written into a cache storage area before being written into a main storage area, write the received data into the cache storage area of the specified target die.

38. ) A computer readable medium having stored therein computer readable program code for data caching in a system including a flash memory device coupled to an external host device, the flash memory device including at least one flash memory die, the flash memory die including a plurality of planes, each plane including a respective cache storage area and a respective main storage area, the program code being operable to:

a) receive data by the flash memory device from an external host device;

b) determine to which main storage area the received data is addressed, thereby specifying one of the plurality of flash memory planes as a target plane for the received data; and

c) whenever the received data is written into a cache storage area before being written into a main storage area, write the received data into the cache storage area of the specified target plane.