Cache controller and cache controlling method

• US 20100107038A1
• Filed: 12/18/2009
• Published: 04/29/2010
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miura, Takashi, Hirano, Takahito, Yamazaki, Iwao
• Granted Patent: US 8,533,565 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc

Abstract

A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.

Claims

1. A cache memory controller comprising:

a data detecting unit that detects a write address in the cache memory into which the store data is stored, an area-to-be-stored of the store data that is to be stored and an area-not-to-be-stored that is not to be stored, when the store data is transmitted from an execution unit;

a data determining unit that determines whether data-to-be-stored that is already written is present in the write address detected by the data detecting unit;

an existing data-not-to-be-stored obtaining unit that obtains, from the data written in the write address, data detected by the data detecting unit and written in the area-not-to-be-stored, as existing data-not-to-be-stored, when the data determining unit determines that the data-to-be-stored is present in the write address;

a store data writing unit that merges the existing data-not-to-be-stored obtained by the existing data-not-to-be-stored obtaining unit with the data-to-be-stored in the area-to-be-stored detected by the data detecting unit to generate new store data, and writes the new store data into the write address detected by the data detecting unit; and

an ECC generating unit that generates an ECC for the new store data written by the store data writing unit into the cache memory, from the new store data generated by the store data writing unit.

2. The cache memory controller according to claim 1 further comprising a data re-detecting unit that, when the data determining unit determines that no data-to-be-stored is present in the write address of the cache memory, detects data-already-stored already stored in the address of the cache memory detected by the data detecting unit after registering the data-to-be-stored thereto, wherein

when the data re-detecting unit detects the data-already-stored already stored in the write address of the cache memory, the store data writing unit merges the data-to-be-stored with the data-already-stored to generate further new store data, and writes the further new store data in the write address detected by the data detecting unit, and

the ECC generating unit generates an ECC for the further new store data written by the store data writing unit into the cache memory, from the further new store data generated by the store data writing unit.

3. The cache memory controller according to claim 1, wherein

when the store data is transmitted from the execution unit, the data detecting unit further detects a write address of a cache memory into which preceding store data transmitted from the execution unit prior to the store data is to be stored, and a preceding area-to-be-stored that is to be stored in the preceding store data,

the data determining unit further determines whether the write address of the store data detected by the data detecting unit makes a match with the write address of the preceding store data,

when the data determining unit determines that the write address of the store data makes a match with the write address of the preceding store data, the store data writing unit merges the existing data-not-to-be-stored, the data-to-be-stored, and the preceding data-to-be-stored in the preceding area-to-be-stored detected by the data detecting unit to generate new store data, and writes the new store data into the write address in the cache memory, and

the ECC generating unit generates an ECC for new data written by the store data writing unit into the cache memory, from the new store data generated by the store data writing unit.

4. A cache memory controlling method suitable comprising:

detecting a write address in the cache memory into which the store data is stored, an area-to-be-stored of the store data that is to be stored and an area-not-to-be-stored that is not to be stored, when the store data is transmitted from an execution unit;

determining whether data-to-be-stored that is already written is present in the write address detected at the detecting;

obtaining, from the data written in the write address, data detected at the detecting and written in the area-not-to-be-stored, as existing data-not-to-be-stored, when it is determined that the data-to-be-stored is present in the write address at the determining;

merging the existing data-not-to-be-stored obtained at the obtaining with the data-to-be-stored in the area-to-be-stored detected at the detecting to generate new store data, and writing the new store data into the write address detected at the detecting; and

generating an ECC for the new store data written at the writing into the cache memory, from the new store data generated at the writing.

5. The cache memory controlling method according to claim 4 further comprising, when it is determined that no data-to-be-stored is present in the write address of the cache memory at the determining, detecting data-already-stored already stored in the address of the cache memory detected at the detecting after registering the data-to-be-stored thereto, wherein

the writing, when the data-already-stored already stored in the write address of the cache memory is detected, includes merging the data-to-be-stored with the data-already-stored to generate further new store data, and writing the further new store data in the write address detected at the detecting, and

the generating includes generating an ECC for the further new store data written at the writing into the cache memory, from the further new store data generated at the writing.

6. The cache memory controlling method according to claim 4, wherein

the detecting, when the store data is transmitted from the execution unit, includes further detecting a write address of a cache memory into which preceding store data transmitted from the execution unit prior to the store data is to be stored, and a preceding area-to-be-stored that is to be stored in the preceding store data,

the determining includes further determining whether the write address of the store data detected at the detecting makes a match with the write address of the preceding store data,

the writing, when it is determined that the write address of the store data makes a match with the write address of the preceding store data at the data determining step, includes merging the existing data-not-to-be-stored, the data-to-be-stored, and the preceding data-to-be-stored in the preceding area-to-be-stored detected at the detecting to generate new store data, and writing the new store data into the write address in the cache memory, and

the ECC generating step includes generating an ECC for new data written at the writing into the cache memory, from the new store data generated at the writing.

7. A computer readable storage medium having stored therein a cache memory controlling program for writing store data received from an execution unit into a cache memory and generating an ECC for the store data, the cache memory controlling program causing a computer to execute a process comprising:

detecting a write address in the cache memory into which the store data is stored, an area-to-be-stored of the store data that is to be stored and an area-not-to-be-stored that is not to be stored, when the store data is transmitted from the execution unit;

determining whether data-to-be-stored that is already written is present in the write address detected at the detecting;

obtaining, from the data written in the write address, data detected at the detecting and written in the area-not-to-be-stored, as existing data-not-to-be-stored, when it is determined that the data-to-be-stored is present in the write address at the determining;

merging the existing data-not-to-be-stored obtained at the obtaining with the data-to-be-stored in the area-to-be-stored detected at the detecting to generate new store data, and writing the new store data into the write address detected at the detecting; and

generating an ECC for the new store data written at the writing into the cache memory, from the new store data generated at the writing.

8. The computer readable storage medium according to claim 7, wherein the cache memory controlling program further comprising, when it is determined that no data-to-be-stored is present in the write address of the cache memory at the determining, detecting data-already-stored already stored in the address of the cache memory detected at the detecting after registering the data-to-be-stored thereto, wherein

the writing, when the data-already-stored already stored in the write address of the cache memory is detected, includes merging the data-to-be-stored with the data-already-stored to generate further new store data, and writing the further new store data in the write address detected at the detecting, and

the generating includes generating an ECC for the further new store data written at the writing into the cache memory, from the further new store data generated at the writing.

9. The computer readable storage medium according to claim 7, wherein

the detecting, when the store data is transmitted from the execution unit, includes further detecting a write address of a cache memory into which preceding store data transmitted from the execution unit prior to the store data is to be stored, and a preceding area-to-be-stored that is to be stored in the preceding store data,

the determining includes further determining whether the write address of the store data detected at the detecting makes a match with the write address of the preceding store data,

the writing, when it is determined that the write address of the store data makes a match with the write address of the preceding store data at the data determining step, includes merging the existing data-not-to-be-stored, the data-to-be-stored, and the preceding data-to-be-stored in the preceding area-to-be-stored detected at the detecting to generate new store data, and writing the new store data into the write address in the cache memory, and

the ECC generating step includes generating an ECC for new data written at the writing into the cache memory, from the new store data generated at the writing.