MULTI-CORE SOC SYNCHRONIZATION COMPONENT

• US 20100107167A1
• Filed: 02/06/2009
• Published: 04/29/2010
• Est. Priority Date: 10/24/2008
• Status: Active Grant

• Current Assignee: National Chung Cheng University
• Original Assignee: National Chung Cheng University
• Inventors: Chen, Tien-Fu, Ku, Wei-Chun, Wen, Chi-Neng
• Granted Patent: US 8,250,580 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 2209/522 Manager
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

The present invention discloses a multi-core SOC synchronization component, which comprises a key administration module, a thread schedule unit supporting data synchronization and thread administration, and an expansion unit serving to expand the memory capacity of the key administration module. The present invention can improve interconnect traffic and prevents from interconnect blocking. The present invention can function as a standard interface of different components. Thus, the present invention can solve the synchronization problem and effectively accelerate product design.

Claims

1. A synchronization component for a multi-core system-on-chip, comprising:

a key administration module storing, distributing and administrating keys, and supporting a data synchronization process when one of said keys is assigned to said data synchronization process;

a thread schedule unit coupled to said key administration module and administrating a threading process when one of said keys is assigned to said threading process; and

an expansion unit providing for expand a memory capacity of said key administration module and coupled to an external memory.

2. The synchronization component for a multi-core system-on-chip according to claim 1, wherein said synchronization component condition is a standard synchronization interface of components of different attributes or configurations.

3. The synchronization component for a multi-core system-on-chip according to claim 1, further comprising a register access interface coupled to said key administration module and at least one register.

4. The synchronization component for a multi-core system-on-chip according to claim 1, wherein said expansion unit further comprises a key-memory address translator and an external memory access interface coupled to said key-memory address translator and said external memory.

5. The synchronization component for a multi-core system-on-chip according to claim 1, wherein said key administration module further comprises:

a key pool storing said keys and supporting an expansion function of said expansion unit;

a key queue supporting data synchronization and thread administration; and

a key manager using said key pool and said key queue to distribute and administrate said keys.

6. The synchronization component for a multi-core system-on-chip according to claim 1, wherein said key contains enable bits and type bits;

said enable bits are used to verify whether said key is in use,said type bits are used to determine whether said key is distributed to said data synchronization process or said threading process.

7. The synchronization component for a multi-core system-on-chip according to claim 1, wherein an operating system of said multi-core system-on-chip executes said data synchronization process and said threading process.

8. The synchronization component for a multi-core system-on-chip according of claim 7, wherein said data synchronization process executed by said operating system includes using said key to determine whether data is accessible.

9. The synchronization component for a multi-core system-on-chip according to claim 7, wherein said data synchronization process executed by said operating system includes using said key to build a critical section for a program and determine whether said program is executable.

10. The synchronization component for a multi-core system-on-chip according to claim 7, wherein said threading process executed by said operating system includes creating a new thread to different components.

11. The synchronization component for a multi-core system-on-chip according to claim 7, wherein said threading process executed by said operating system includes not executing an added thread until execution of at least one assigned thread is completed.

12. The synchronization component for a multi-core system-on-chip according to claim 7, wherein said threading process executed by said operating system includes executing an added thread until a related thread is executed to an identical point and then executing said added thread and said related thread simultaneously.

13. The synchronization component for a multi-core system-on-chip according to claim 7, wherein said threading process executed by said operating system includes informing a standby thread that execution of at least one assigned thread is completed.