Method of Fabricating A Fin Field Effect Transistor (FinFET) Device

• US 20100109086A1
• Filed: 11/06/2008
• Published: 05/06/2010
• Est. Priority Date: 11/06/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Han, Beom-Mo, Song, Seung-Chul, Abu-Rahma, Mohamed Hassan
• Granted Patent: US 7,829,951 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.

Claims

1. A method comprising:

depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width;

depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure, the second dummy structure having a third sidewall and a fourth sidewall separated by a second width, wherein the second width is substantially greater than the first width;

wherein the first dummy structure is used to form a first pair of fins separated by approximately the first width; and

wherein the second dummy structure is used to form a second pair of fins separated by approximately the second width.

2. The method of claim 1, further comprising:

depositing a first insulating material to form a first insulating spacer adjacent to the first sidewall and to form a second insulating spacer adjacent to the second sidewall;

depositing a second insulating material to form a third insulating spacer adjacent to the third sidewall and a fourth insulating spacer adjacent to the fourth sidewall;

removing the first dummy structure from the silicon substrate; and

removing the second dummy structure from the silicon substrate.

3. The method of claim 2, further comprising removing a portion of at least one of the third insulating spacer and the fourth insulating spacer.

4. The method of claim 3, further comprising depositing contact pad structures over at least a portion of at least one of the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer.

5. The method of claim 4, further comprising performing a silicon etch using the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer as etch masks to form a plurality of fins.

6. The method of claim 5, wherein the plurality of fins are implemented in a six-transistor (6T) static random access memory (SRAM) bitcell.

7. The method of claim 6, further comprising forming at least one field effect transistor (FET) having a first gate structure to modulate a current through at least one fin of the plurality of fins.

8. The method of claim 7, wherein the at least one field effect transistor is one of a pull-up FET, a pull-down FET and a pass-gate FET.

9. The method of claim 5, wherein at least one fin of the plurality of fins is less than fifteen nanometers wide.

10. The method of claim 5, further comprising:

forming a pull-down FET using a first gate to modulate a current through a fin formed using the first insulating spacer and the second insulating spacer; and

forming a pull-up FET using a second gate to modulate a current through a fin formed using the third insulating spacer or the fourth insulating spacer.

11. An electronic device comprising:

a first pair of fins comprising first and second protrusions on an etched silicon substrate, the first protrusion substantially parallel to the second protrusion and separated by a first width;

a second pair of fins comprising third and fourth protrusions separated by a second width on the etched silicon substrate, wherein the second width is different than the first width;

a third pair of fins comprising fifth and sixth protrusions separated by a third width on the etched silicon substrate;

wherein the second pair of fins is located between the first pair of fins and the third pair of fins;

wherein the first and second pair of fins are formed by applying a lithographic mask with dummy structures having different sizes.

12. The electronic device of claim 11, wherein the second width is substantially greater than the first width and wherein the second width is greater than the third width.

13. The electronic device of claim 11, wherein the third width is same as the first width.

14. The electronic device of claim 11, further comprising contact pad structures coupled to at least a portion of at least one of the first pair of fins, the second pair of fins, and the third pair of fins.

15. The electronic device of claim 11, further comprising:

a pull-down field effect transistor (FET) using a first gate to modulate a current through the first protrusion and the second protrusion or through the fifth protrusion and the sixth protrusion; and

a pull-up FET formed using a second gate to modulate a current through the third protrusion or the fourth protrusion.

16. The electronic device of claim 11, further comprising a pull-up FET having a gate to modulate a current through the first pair of fins.

17. The electronic device of claim 11, further comprising a pull-down FET having a gate to modulate a current through the second pair of fins.

18. The electronic device of claim 11, further comprising a pass-gate FET having a gate to modulate a current through the first pair of fins in parallel with a pull-down FET.

19. A method of fabricating a static random access memory (SRAM), the method comprising:

forming a first dummy structure using a lithographic mask, the first dummy structure having a first width and first laterally opposed sidewalls;

forming a second dummy structure concurrently with forming the first dummy structure, the second dummy structure having a second width substantially greater than the first width, the second dummy structure having second laterally opposed sidewalls;

forming a third dummy structure concurrently with the first dummy structure, the third dummy structure having the first width, the third dummy structure having third laterally opposed sidewalls;

depositing a first insulating material on the first laterally opposed sidewalls to form a first insulating spacer and a second insulating spacer;

depositing a second insulating material on the second laterally opposed sidewalls to form a third insulating spacer and a fourth insulating spacer;

depositing a third insulating material on the third laterally opposed sidewalls to form a fourth insulating spacer and a fifth insulating spacer;

removing the first dummy structure;

removing the second dummy structure; and

removing the third dummy structure.

20. The method of claim 19, further comprising performing an etch to form a first fin under the first insulating spacer, a second fin under the second insulating spacer, a third fin under the third insulating spacer, a fourth fin under the fourth insulating spacer, a fifth fin under the fifth insulating spacer, and a sixth fin under the sixth insulating spacer.

21. The method of claim 20, further comprising:

forming a first pull-down field effect transistor (FET) using a first gate to modulate a first current through the first fin and through the second fin;

forming a first pass-gate FET using a second gate to modulate a second current through the first fin and through the second fin in parallel with the first pull-down FET;

forming a first pull-up FET using the second gate to modulate a third current through the third fin;

forming a second pull-up FET using a third gate to modulate a fourth current through the fourth fin;

forming a second pull-down FET using the third gate to modulate a fifth current through the fifth fin and through the sixth fin; and

forming a second pass-gate FET using a fourth gate to modulate a sixth current through the fifth fin and through the sixth fin in parallel with the second pull-down FET.

22. The method of claim 20, further comprising removing at least a portion of at least one of the third fin and the fourth fin.

23. A method comprising:

depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width, wherein the first width is between 10 and 30 nanometers;

depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure, the second dummy structure having a third sidewall and a fourth sidewall separated by a second width, wherein the second width is between 40 and 70 nanometers;

depositing a first insulating material to form a first insulating spacer adjacent to the first sidewall and to form a second insulating spacer adjacent to the second sidewall;

depositing a second insulating material to form a third insulating spacer adjacent to the third sidewall and a fourth insulating spacer adjacent to the fourth sidewall;

removing the first dummy structure from the silicon substrate; and

removing the second dummy structure from the silicon substrate.

24. The method of claim 23, further comprising:

removing a portion of at least one of the third insulating spacer and the fourth insulating spacer; and

depositing contact pad structures over at least a portion of at least one of the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer.

25. The method of claim 24, further comprising performing an etch using the first insulating spacer, the second insulating spacer, the third insulating spacer, and the fourth insulating spacer as etch masks to form a plurality of fins.