High density spin-transfer torque MRAM process

• US 20100109106A1
• Filed: 10/31/2008
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: MagiQ Technologies, Incorporated
• Inventors: Liu, Daniel, Zhong, Tom, Kan, Wai-Ming Johnson, Zhong, Adam, Torng, Chyu-Jiuh, Xiao, Rongfu
• Granted Patent: US 7,884,433 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment

Abstract

A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

Claims

1. A STT-MRAM structure formed on a substrate having a CMOS metal layer including a plurality of CMOS landing pads in a device region and a plurality of CMOS connection pads outside the device region that are separated by and coplanar with a first dielectric layer, comprising:

(a) a stack of dielectric layers that are formed sequentially from bottom to top on the substrate, comprising;

a first etch stop layer, a second dielectric layer, a metal separation (VAM) dielectric layer, a MTJ ILD layer, a second etch stop layer, and a BIT ILD layer;

(b) a plurality of intermediate via contacts (VAC) each having a first width that are formed within the first etch stop layer and second dielectric layer in the device region wherein each of said VAC is in electrical contact with an underlying CMOS landing pad, and has a top surface coplanar with said second dielectric layer;

(c) a plurality of VAM pads each having a second width greater than said first width, a bottom surface contacting and completely covering a top surface of a VAC, and a top surface that is coplanar with said VAM dielectric layer;

(d) a plurality of MTJ elements each having a bottom surface contacting the top surface of a VAM pad and a top hard mask surface coplanar with said MTJ ILD layer; and

(e) a BIT line metal layer, comprising;

(1) a plurality of BIT connection vias formed coplanar with said MTJ ILD layer and within the first etch stop layer, second dielectric layer, VAM dielectric layer, and MTJ ILD layer wherein at least one BIT connection via contacts each CMOS connection pad;

(2) a plurality of BIT line connection pads formed coplanar with said BIT ILD layer and within said second etch stop layer and BIT ILD layer wherein each of said BIT line connection pads contacts a top surface of at least one BIT connection via to provide an electrical connection to an underlying CMOS connection pad; and

(3) a plurality of BIT lines formed coplanar with said BIT ILD layer in the device region wherein each of said BIT lines is aligned above a MTJ and is in electrical contact with said top hard mask surface to provide an electrical connection between a BIT line and an underlying CMOS landing pad through a stack of layers represented by a MTJ/VAM/VAC configuration.

2. The STT-MRAM of claim 1 wherein the first etch stop layer is comprised of silicon nitride or SiCN and has a thickness between about 300 and 1500 Angstroms, and the second etch stop layer is comprised of silicon nitride and has a thickness from about 300 to 1000 Angstroms.

3. The STT-MRAM of claim 1 wherein the BIT ILD layer is comprised of silicon oxide and has a thickness between about 1000 to 5000 Angstroms.

4. The STT-MRAM of claim 1 further comprised of a diffusion barrier layer formed between each VAC and an underlying CMOS landing pad, a diffusion barrier layer between each BIT connection via and CMOS connection pad, and a diffusion barrier layer between each BIT line and underlying MTJ element.

5. The STT-MRAM of claim 1 wherein each of the plurality of VAM pads has a thickness between about 100 and 500 Angstroms and is a single layer or composite layer comprised of one or more of Ta, TaN, and other conductive materials.

6. The STT-MRAM of claim 1 wherein the top hard mask surface of the MTJ is comprised of Ta.

7. The STT-MRAM of claim 1 wherein each of the plurality of VAM pads has a circular, oval, or rectangular shape from a top-down view.

8. The STT-MRAM of claim 1 further comprised of a plurality of dummy VAC elements formed coplanar with the plurality of VACs, a plurality of dummy VAM pads formed coplanar with the plurality of VAM pads, and a plurality of dummy MTJs that are coplanar with the plurality of active MTJs and are not electrically connected to a CMOS landing pad.

9. The STT-MRAM of claim 1 wherein each VAC is comprised of Cu having a thickness from about 500 to 3000 Angstroms.

10. A method of fabricating a STT-MRAM on a substrate having a CMOS metal layer including a plurality of CMOS landing pads in a device region and a plurality of CMOS connection pads outside the device region that are separated by and are coplanar with a first dielectric layer, comprising:

(a) sequentially forming a first etch stop layer and a second dielectric layer on the first dielectric layer and CMOS metal layer;

(b) forming a plurality of intermediate via contacts (VAC) each having a first width within the first etch stop layer and second dielectric layer in the device region wherein each of said VAC is in electrical contact with an underlying CMOS landing pad, and has a top surface coplanar with said second dielectric layer;

(c) forming a plurality of metal separation (VAM) pads on the second dielectric layer and separated by openings wherein each of said VAM pads has a second width greater than said first width and a bottom surface contacting and completely covering a top surface of a VAC, and forming a VAM dielectric layer that is coplanar with a top surface of each VAM pad and fills the openings between the VAM pads;

(d) forming a plurality of MTJ elements each having a bottom surface that contact a top surface of an underlying VAM pad and a top hard mask surface, said MTJ elements are separated by openings that are subsequently filled with a MTJ ILD layer which is then planarized to be coplanar with said top hard mask surface;

(e) sequentially depositing a second etch stop layer and a BIT ILD layer on the MTJ ILD layer and plurality of MTJ elements; and

(f) performing a dual damascene process, comprising;

(1) forming a plurality of BIT connection via openings in the BIT ILD layer that extend through the second etch stop layer, MTJ ILD layer, VAM dielectric layer, and second dielectric layer and stop on the first etch stop layer above each of the plurality of CMOS connections pads;

(2) simultaneously forming a plurality of a first trenches in the BIT ILD layer and second etch stop layer outside the device region wherein each first trench connects with at least one BIT connection via opening, removing the first etch stop layer exposed by BIT connection via openings above the CMOS connection pads, and forming a plurality of second trenches in the BIT ILD layer and second etch stop layer in the device region wherein each second trench uncovers a top hard mask surface of a MTJ; and

(3) depositing a conformal diffusion barrier layer within the first trenches, second trenches, and in the plurality of BIT connection vias, depositing a BIT metal layer on the conformal diffusion barrier layer to fill the plurality of first and second trenches and plurality of BIT connection vias, and planarizing the BIT metal layer to become coplanar with the BIT ILD layer.

11. The method of claim 10 wherein the first etch stop layer is comprised of silicon nitride or SiCN and has a thickness between about 300 and 1500 Angstroms, and the second etch stop layer is comprised of silicon nitride and has a thickness from about 300 to 1000 Angstroms.

12. The method of claim 10 wherein forming a plurality of MTJ elements comprises at least one anneal step to set the magnetization direction of a pinned layer therein.

13. The method of claim 10 wherein the BIT ILD layer is comprised of silicon oxide and has a thickness between about 1000 to 5000 Angstroms.

14. The method of claim 10 wherein the top hard mask surface is comprised of Ta.

15. The method of claim 10 wherein forming a plurality of VAC is comprised of a single damascene process in which a plurality of VAC openings is formed in the first etch stop layer and second dielectric layer following by deposition of a diffusion barrier layer as a liner in the VAC openings and then depositing a metal on the diffusion barrier layer to fill the VAC openings.

16. The method of claim 10 wherein each of the plurality of VAM pads has a circular, oval, or rectangular shape from a top-down view

17. The method of claim 10 wherein step (b) is further comprised of forming a plurality of dummy VAC elements that are coplanar with said VAC elements, step (c) is further comprised of forming a plurality of dummy VAM pads that are coplanar with said VAM pads, and step (d) is further comprised of forming a plurality of dummy MTJs that are coplanar with said MTJ elements but are not electrically connected to a CMOS landing pad.

18. The method of claim 10 wherein each CMOS landing pad is electrically connected to a CMOS transistor in a sub-structure of the substrate.

19. The method of claim 10 wherein each of the plurality of VAM pads has a thickness between about 100 and 500 Angstroms and is a single layer or composite layer comprised of one or more of Ta, TaN, and other conductive materials.

20. The method of claim 10 wherein each VAC is comprised of Cu having a thickness from about 500 to 3000 Angstroms.