SINGLE CRYSTAL SILICON STRUCTURES

• US 20100109120A1
• Filed: 01/14/2010
• Published: 05/06/2010
• Est. Priority Date: 06/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wells, David H., Fucsko, Janos, Lee, Whonchee, Flynn, Patrick
• Granted Patent: US 8,159,050 B2
• Time in Patent Office: Days
• US Class Current: 257/507
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Claims

1. A semiconductor device structure comprising:

a single crystal silicon substrate; and

a plurality of single crystal silicon islands isolated from the single crystal silicon substrate and from each other by an oxide material, wherein the plurality of single crystal silicon islands are not oxidized during formation thereof.

2. The semiconductor device structure of claim 1, wherein each of the plurality of single crystal silicon islands is disposed on one of a plurality of pillars comprising the oxide material.

3. The semiconductor device structure of claim 2, wherein each of the plurality of pillars extends perpendicularly between a surface of the single crystal silicon substrate and a base of one of the plurality of single crystal silicon islands.

4. The semiconductor device structure of claim 2, wherein an outer perimeter of each of the single crystal silicon islands laterally extends beyond an outer perimeter of an underlying one of the plurality of pillars.

5. The semiconductor device structure of claim 2, wherein adjacent pairs of the plurality of pillars are spaced apart by a cavity defined by beveled edges.

6. The semiconductor device structure of claim 2, wherein each of the single crystal silicon islands is defined by beveled edges.

7. The semiconductor device structure of claim 1, wherein the semiconductor device structure further comprises a liner material overlying an upper surface and sidewalls of each of the plurality of single crystal silicon islands.

8. The semiconductor device structure of claim 7, wherein portions of the plurality of single crystal silicon islands underlying the liner material remain unoxidized.

9. A semiconductor device structure, comprising a plurality of single crystal silicon structures, each disposed on a pillar extending perpendicularly between a surface of the single crystal silicon substrate and a base of one of the plurality of single crystal silicon islands.

10. The semiconductor device structure of claim 9, wherein an outer perimeter of the silicon structure laterally extends beyond an outer perimeter of the at least one pillar.

11. The semiconductor device structure of claim 9, further comprising a liner overlying an upper surface each of the plurality of single crystal silicon structures and extending at least partially over sidewalls thereof.

12. The semiconductor device structure of claim 9, wherein the pillar is spaced apart from another pillar by a trench defined by substantially square edges.

13. A semiconductor device structure, comprising:

a single crystal silicon substrate; and

at least one undercut defined by concave square corners within the single crystal silicon substrate.

14. The semiconductor device structure of claim 13, further comprising a via in a <

100>

direction in the single crystal silicon substrate and extending from an upper surface of the single crystal silicon substrate to the at least one undercut.

15. The semiconductor device structure of claim 14, further comprising a liner overlying the upper surface of the single crystal silicon substrate and extending at least partially onto sidewalls of the via.

16. The semiconductor device structure of claim 13, wherein the at least one undercut is formed by exposing the single crystal silicon substrate to a solution comprising NH₄F, H₂O₂ and H₃PO₄ in a volumetric ratio of about 4:

2;

3

17. The semiconductor device structure of claim 13, wherein the at least one undercut is disposed adjacent another undercut cavity in the single crystalline silicon substrate.

18. A semiconductor device structure, comprising:

a single crystal silicon substrate having at least one trench therein; and

at least one cavity opening from the at least one trench and defined by substantially square corners in the silicon crystal silicon substrate.

19. The semiconductor device structure of claim 18, wherein the at least one trench is formed in the <

100>

direction in the single crystal silicon substrate.

20. The semiconductor device structure of claim 18, wherein the at least one cavity lacks beveled edges.