CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

• US 20100109132A1
• Filed: 03/31/2009
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lee, Jung, An, Jaesun, Ko, Dongkyun
• Granted Patent: US 8,093,690 B2
• Time in Patent Office: Days
• US Class Current: 257/660
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2203/0415 : Small preforms other than balls, e.g. discs, cylinders or pillars
• CPC Class Codes: H05K 3/0032 : of organic insulating material
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Claims

1. A chip package, comprising:

a semiconductor substrate;

at least a chip disposed on the semiconductor substrate and electrically connected to the semiconductor substrate;

a molding compound disposed over the semiconductor substrate, at least encapsulating the chip, and a portion of the semiconductor substrate; and

a shielding layer, disposed over the molding compound, wherein the shielding layer includes a plurality of conductive connectors disposed on the semiconductor substrate and around the chip, the conductive connectors are arranged surrounding the chip in a ring fashion, and the chip is separated from the conductive connectors and the shielding layer is electrically connected to the semiconductor substrate through the conductive connectors.

2. The chip package as claimed in claim 1, wherein the conductive connectors are individual metal studs separate from one another and exposed from sidewalls of the molding compound.

3. The chip package as claimed in claim 1, wherein the conductive connectors are individual metal studs separate from one another, located within the molding compound without being exposed from sidewalls of the molding compound.

4. The chip package as claimed in claim 1, wherein the conductive connectors are individual plated via structures separate from one another and exposed from sidewalls of the molding compound.

5. The chip package as claimed in claim 1, wherein the conductive connectors are individual plated via structures separate from one another, located within the molding compound without being exposed from sidewalls of the molding compound.

6. The chip package as claimed in claim 1, wherein the conductive connectors are solid ring structures without being exposed from sidewalls of the molding compound.

7. The chip package as claimed in claim 1, wherein the conductive connectors are hollow ring structures without being exposed from sidewalls of the molding compound.

8. The chip package as claimed in claim 1, wherein sidewalls of the molding compound are completely covered by the conductive connectors.

9. The chip package as claimed in claim 8, wherein the sidewalls of the molding compound are tilted.

10. The chip package as claimed in claim 1, wherein the shielding layer is electrically connected to the semiconductor substrate through the conductive connectors and at least a ground via of the semiconductor substrate.

11. A manufacturing method of a chip package, comprising:

providing a matrix substrate having a plurality of substrate units, wherein each substrate unit is defined by a plurality of sawing lines;

disposing at least a chip on each substrate unit, wherein the chip is electrically connected to the substrate unit;

forming a molding compound over the matrix substrate to encapsulate the chips;

performing a marking process to form a plurality of vias or trenches within the molding compound by removing portions of the molding compound until a top surface of each substrate unit is exposed;

forming a shielding layer over the molding compound to cover the molding compound, and simultaneously forming a plurality of connectors over the vias or the trenches and cover the exposed top surface of each substrate unit; and

performing a singulation process to obtain a plurality of chip packages.

12. The method as claimed in claim 11, wherein the connectors are formed as studs filling up the vias.

13. The method as claimed in claim 12, wherein the studs are arranged on the sawing lines of the matrix substrate and on boundary lines of each substrate unit and the singulation process cuts through the studs and the matrix substrate.

14. The method as claimed in claim 12, wherein the studs are disposed between boundary lines of each substrate unit and the chip, and the singulation process cuts through the matrix substrate but not the studs.

15. The method as claimed in claim 11, wherein the connectors are formed by partially filling the vias as plated via structures.

16. The method as claimed in claim 15, wherein the plated via structures are arranged on the sawing lines of the matrix substrate and on boundary lines of each substrate unit, and the singulation process cuts through the plated via structures and the matrix substrate.

17. The method as claimed in claim 15, wherein the plated via structures are arrange between the chip and boundary lines of each substrate unit, and the singulation process cuts through the matrix substrate but not the plated via structures.

18. The method as claimed in claim 11, wherein the connectors are formed as ring structures filling up the trenches.

19. The method as claimed in claim 18, wherein the ring structures are arranged on the sawing lines of the matrix substrate and on boundary lines of each substrate unit, and the singulation process cuts through the ring structures and the matrix substrate.

20. The method as claimed in claim 18, wherein the ring structures are arrange between the chip and boundary lines of each substrate unit, and the singulation process cuts through the matrix substrate but not the ring structures.

21. The method as claimed in claim 11, wherein the connectors are formed as hollow ring structures partially filling up the trenches.

22. The method as claimed in claim 21, wherein the hollow ring structures are arranged on the sawing lines of the matrix substrate and on boundary lines of each substrate unit, and the singulation process cuts through the hollow ring structures and the matrix substrate.

23. The method as claimed in claim 21, wherein the hollow ring structures are arranged between the chip and boundary lines of each substrate unit, and the singulation process cuts through the matrix substrate but not the hollow ring structures.