DRIVER CIRCUIT AND DISPLAY DEVICE

• US 20100110623A1
• Filed: 10/27/2009
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, KOYAMA, Jun
• Granted Patent: US 9,842,859 B2
• Time in Patent Office: Days
• US Class Current: 361/679.10
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

The driver circuit includes an inverter circuit having a first thin film transistor including a first oxide semiconductor film and a second transistor including a second oxide semiconductor film. The first thin film transistor and the second thin film transistor are enhancement transistors, in which a silicon oxide film including an OH group is provided on and in contact with the first oxide semiconductor film and the second oxide semiconductor film, and a silicon nitride film is provided on and in contact with the silicon oxide film.

Claims

1. A driver circuit comprising:

an inverter circuit including a first enhancement transistor and a second enhancement transistor;

a silicon oxide film including an OH group on and in contact with a first oxide semiconductor film of the first enhancement transistor and a second oxide semiconductor film of the second enhancement transistor; and

a silicon nitride film on and in contact with the silicon oxide film.

2. The driver circuit according to claim 1,

wherein the first enhancement transistor comprises a gate terminal and a first terminal, which are electrically connected to a wiring for supplying high power supply potential, and

wherein the second enhancement transistor comprises a gate terminal supplied with an input signal, a first terminal electrically connected to a second terminal of the first enhancement transistor, and a second terminal electrically connected to a wiring for supplying low power supply potential.

3. The driver circuit according to claim 1,

wherein each of the first enhancement transistor and the second enhancement transistor is a bottom-gate transistor, an inverted staggered transistor, or a co-planar transistor.

4. The driver circuit according to claim 1,

wherein a third oxide semiconductor film is provided between the wiring for supplying the high power supply potential and the first oxide semiconductor film, and

wherein a fourth oxide semiconductor film is provided between the wiring for supplying the low power supply potential and the second oxide semiconductor film.

5. The driver circuit according to claim 1,

wherein each of the first oxide semiconductor film and the second oxide semiconductor film comprises at least one of indium, gallium, and zinc.

6. A driver circuit comprising:

an inverter circuit including a first enhancement transistor and a second enhancement transistor;

a switch including a third enhancement transistor, the switch being electrically connected with the inverter circuit;

a silicon oxide film including an OH group on and in contact with a first oxide semiconductor film of the first enhancement transistor and a second oxide semiconductor film of the second enhancement transistor; and

a silicon nitride film on and in contact with the silicon oxide film.

7. The driver circuit according to claim 6,

wherein the first enhancement transistor comprises a gate terminal and a first terminal, which are electrically connected to a wiring for supplying high power supply potential, and

wherein the second enhancement transistor comprises a gate terminal supplied with an input signal, a first terminal electrically connected to a second terminal of the first enhancement transistor, and a second terminal electrically connected to a wiring for supplying low power supply potential.

8. The driver circuit according to claim 6,

wherein on/off of the switch is controlled by a clock signal or an inverted clock signal.

9. The driver circuit according to claim 6,

wherein each of the first enhancement transistor, the second enhancement transistor, and the third enhancement transistor is a bottom-gate transistor, an inverted staggered transistor, or a co-planar transistor.

10. The driver circuit according to claim 6,

wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film comprises at least one of indium, gallium, and zinc.

11. A driver circuit comprising:

an inverter circuit including a first enhancement transistor and a second enhancement transistor;

a switch including a third enhancement transistor, the switch being electrically connected with the inverter circuit;

a first silicon oxide film including an OH group on and in contact with a first oxide semiconductor film of the first enhancement transistor and a second oxide semiconductor film of the second enhancement transistor;

a first silicon nitride film on and in contact with the first silicon oxide film;

a second silicon oxide film including an OH group on and in contact with a third oxide semiconductor film of the third enhancement transistor; and

a second silicon nitride film on and in contact with the second silicon oxide film.

12. The driver circuit according to claim 11,

wherein the first enhancement transistor comprises a gate terminal and a first terminal, which are electrically connected to a wiring for supplying high power supply potential, and

wherein the second enhancement transistor comprises a gate terminal supplied with an input signal, a first terminal electrically connected to a second terminal of the first enhancement transistor, and a second terminal electrically connected to a wiring for supplying low power supply potential.

13. The driver circuit according to claim 11,

wherein on/off of the switch is controlled by a clock signal or an inverted clock signal.

14. The driver circuit according to claim 11,

wherein each of the first enhancement transistor, the second enhancement transistor, and the third enhancement transistor is a bottom-gate transistor, an inverted staggered transistor, or a co-planar transistor.

15. The driver circuit according to claim 11,

wherein each of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film comprises at least one of indium, gallium, and zinc.

16. A display device comprising:

a driver circuit over a substrate, the driver circuit comprising;

an inverter circuit including a first enhancement transistor and a second enhancement transistor;

a silicon oxide film including an OH group on and in contact with a first oxide semiconductor film of the first enhancement transistor and a second oxide semiconductor film of the second enhancement transistor;

a silicon nitride film on and in contact with the silicon oxide film; and

a pixel portion including a third enhancement transistor over the substrate.

17. The display device according to claim 16,

wherein the first enhancement transistor comprises a gate terminal and a first terminal, which are electrically connected to a wiring for supplying high power supply potential, and

wherein the second enhancement transistor comprises a gate terminal supplied with an input signal, a first terminal electrically connected to a second terminal of the first enhancement transistor, and a second terminal electrically connected to a wiring for supplying low power supply potential.

18. The display device according to claim 16,

wherein each of the first enhancement transistor, the second enhancement transistor, and the third enhancement transistor is a bottom-gate transistor, an inverted staggered transistor, or a co-planar transistor.

19. The display device according to claim 16,

wherein each of the first oxide semiconductor film, the second oxide semiconductor film and the third oxide semiconductor film comprises at least one of indium, gallium, and zinc.

20. The display device according to claim 16,

wherein the substrate is a glass substrate.

21. An electronic device provided with the display device according to claim 16.