VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD

• US 20100110756A1
• Filed: 10/30/2008
• Published: 05/06/2010
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Liu, Hongyue, Lee, Brian, Carter, Andrew John Gjevre, Khoury, Maroun Georges
• Granted Patent: US 7,936,583 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

Claims

1. A method comprising:

switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the variable resistive data cell in a first direction, the write current provided by a transistor being electrically coupled to the variable resistive data cell and a source line, the write current passing through the transistor in punchthrough mode; and

switching the variable resistive data cell from a low resistance state to a high resistance state by passing a write current through the variable resistive data cell in a second direction opposing the first direction, the write current provided by the transistor, the write current passing through the transistor in punchthrough mode.

2. A method according to claim 1, wherein the transistor is a NMOS transistor or a PMOS transistor.

3. A method according to claim 1, wherein the variable resistive data cell is a magnetic tunnel junction data cell.

4. A method according to claim 1, wherein the write current in the first direction has about the same magnitude as the write current in the second direction.

5. A method according to claim 3, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

6. A method according to claim 1, further comprising passing a read current through the variable resistive data cell by activating a gate of the transistor.

7. A method according to claim 1, further comprising passing a read current through the variable resistive data cell, the read current passing through the transistor in punchthrough mode.

8. A method according to claim 1, wherein the write current in the first direction and the write current in the second direction is formed by a voltage difference across a source region and drain region of the transistor having a magnitude equal to or greater than a punchthrough voltage for the transistor.

9. A method comprising:

precharging a plurality of bit lines and a plurality of source lines to a precharge voltage being less than a punchthrough voltage of a transistor, the plurality of source lines intersecting with the plurality of bit lines and forming a cross-point array, and a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising a variable resistive data cell and the transistor, the transistor is electrically connected between the variable resistive data cell and one of the plurality of source lines; and

writing a first data state to one or more variable resistive data cells along a selected bit line by applying the punchthrough voltage across the selected bit line and one or more selected source lines to pass a first data state write current through the transistor by merging a source depletion region and a drain depletion region in the transistor substrate in punchthrough mode.

10. A method according to claim 9, further comprising writing a second data state to one or more variable resistive data cells along a selected bit line by applying the punchthrough voltage across the selected bit line and one or more selected source lines to pass a second data state write current through the transistor in punchthrough mode, the second data state write current opposing the first data state write current.

11. A method according to claim 10, wherein the first data state write current has about the same magnitude as the second data state write current.

12. A method according to claim 9, wherein the transistor is a NMOS transistor or a PMOS transistor.

13. A method according to claim 9, wherein the variable resistive data cell is a magnetic tunnel junction data cell.

14. A method according to claim 13, wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.

15. A method according to claim 9, further comprising passing a read current through the variable resistive data cell by activating a gate of the transistor.

16. A method according to claim 9, further comprising passing a read current through the variable resistive data cell, the read current passing through the transistor in punchthrough mode.

17. A method according to claim 9, wherein the first data state write current and the second data state write current is formed by a voltage difference across the source depletion region and the drain depletion region and having a magnitude equal to or greater than the punchthrough voltage for the transistor.

18. A method comprising:

applying a punchthrough voltage across a first bit line and a source line to form a write current to switch a first variable resistive data cell from a high resistance state to a low resistance state, the write current passing through a first transistor being electrically coupled to the first variable resistive data cell and the first bit line, the write current passing through the transistor in punchthrough mode;

activating a common transistor to allow the write current to pass through the common transistor, the common transistor electrically coupled to the source line and the first variable resistive data cell, the common transistor electrically coupled to a second variable resistive data cell, the second variable resistive data cell electrically coupled to a second bit line via a second transistor.

19. A method according to claim 18, wherein the first and second variable resistive data cells are spin-transfer torque data cells.

20. A method according to claim 18, wherein the second bit line is grounded and current does not flow through the second transistor.