Word Line Voltage Control in STT-MRAM

• US 20100110775A1
• Filed: 11/05/2008
• Published: 05/06/2010
• Est. Priority Date: 11/05/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sani, Mehdi Hamidi, Kang, Seung H., Yoon, Sei Seung
• Granted Patent: US 8,107,280 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.

Claims

1. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor, wherein the bit cell is coupled to a bit line and a source line; and

a word line driver coupled to a gate of the word line transistor, wherein the word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.

2. The STT-MRAM of claim 1, wherein the word line voltage is clamped at or below a limit voltage after reaching the transition voltage.

3. The STT-MRAM of claim 2, wherein the word line voltage is decreased after reaching the transition voltage.

4. The STT-MRAM of claim 1, wherein the transition voltage represents a transition between a low Vdd region and a high Vdd region.

5. The STT-MRAM of claim 1, further comprising:

a write driver configured to provide an electrical signal to the bit cell to store a logic state in the bit cell; and

at least one write isolation element coupled in series with the write driver between the bit line and source line, wherein the write isolation element is configured to isolate the write driver during a read operation.

6. The STT-MRAM of claim 4, wherein the write driver comprises:

first and second inverters coupled in series between a data input and the bit line; and

a third inverter coupled in series between the data input and the source line.

7. The STT-MRAM of claim 1, further comprising:

a read isolation element interposed between the bit cell and a sense amplifier, wherein the isolation element is configured to selectively isolate the sense amplifier from the bit line during a write operation.

8. The STT-MRAM of claim 6, wherein the read isolation element is at least one of a switch, a transmission gate, or a multiplexer.

9. The STT-MRAM of claim 1, further comprising:

a voltage pump circuit configured to generate the word line voltage from the supply voltage.

10. The STT-MRAM of claim 9, further comprising:

a level detector configured to control the voltage pump circuit to generate the word line voltage from the supply voltage.

11. A method for read and write operations in a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

applying a first voltage to a gate of a word line transistor of a bit cell during a write operation, wherein the first voltage is higher than a supply voltage if the supply voltage is lower than a transition voltage; and

applying a second voltage to the word line transistor during a write operation, wherein the second voltage is lower than the supply voltage if the supply voltage is higher than a transition voltage.

12. The method of claim 11, further comprising:

clamping the word line voltage at or below a limit voltage beyond the transition voltage to provide the second voltage.

13. The method of claim 11, further comprising:

decreasing the second voltage after reaching the transition voltage to provide the second voltage.

14. The method of claim 11, wherein the transition voltage represents a transition between a low Vdd region and a high Vdd region.

15. The method of claim 11, further comprising:

pumping the supply voltage to generate the first voltage using a charge pump circuit.

16. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

means for applying a first voltage to a gate of a word line transistor of a bit cell during a write operation, wherein the first voltage is higher than a supply voltage if the supply voltage is lower than a transition voltage; and

means for applying a second voltage to the word line transistor during a write operation, wherein the second voltage is lower than the supply voltage if the supply voltage is higher than a transition voltage.

17. The STT-MRAM of claim 16, further comprising:

means for clamping the word line voltage at or below a limit voltage after reaching the transition voltage to provide the second voltage.

18. The STT-MRAM of claim 16, further comprising:

means for decreasing the second voltage after reaching the transition voltage to provide the second voltage.

19. The STT-MRAM of claim 16, wherein the transition voltage represents a transition between a low Vdd region and a high Vdd region.

20. The STT-MRAM of claim 16, further comprising:

means for pumping the supply voltage to generate the first voltage using a charge pump circuit.