SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE OPERATION METHOD
First Claim
1. A semiconductor memory device including:
- a plurality of word lines;
a plurality of bit lines which are provided in a direction intersecting the plurality of word lines;
a plurality of memory cells which are arranged in a matrix pattern that corresponds to intersections between the plurality of word lines and the plurality of bit lines;
a plurality of sense amplifiers which are associated with the plurality of bit lines on a one-on-one basis;
a plurality of switch circuits each of which belongs to one of first to n-th (n is an integer equal to or larger than
2) groups, and which are associated with the plurality of bit lines and with the plurality of sense amplifiers on a one-on-one basis, each switch circuit connecting its associated bit line and sense amplifier to each other when turned on; and
a timing control section for controlling at least timing of the sense amplifiers and the switch circuits which, in reading stored data out of the memory cells, executes control in which the plurality of sense amplifiers are disabled while the plurality of switch circuits are turned on for a given period of time, the plurality of switch circuits are turned off and then the plurality of sense amplifiers are enabled, and, when a given period of time elapses since the relevant sense amplifiers are enabled, the switch circuits belonging to the first to n-th groups are sequentially turned on group by group at given time intervals.
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Accused Products
Abstract
Provided is a destructive readout semiconductor memory device capable of avoiding concentration of a writeback current, in which a switch circuit (24) is provided between each bit line (21) and each sense amplifier (26). In writeback, the switch circuits are turned on at staggered time points. In readout, the switch circuits are turned on to read memory cell data to the sense amplifiers while the sense amplifiers are turned off, and the switch circuits are then turned off once. After that, the sense amplifiers are turned on to amplify the read data. The switch circuits are subsequently divided into groups and turned on again to write back the data amplified by the sense amplifiers to the memory cells. The switch circuits are divided into groups to be turned on at staggered time points during the writeback, to thereby avoid concentration of the writeback current in one time period.
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Citations
9 Claims
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1. A semiconductor memory device including:
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a plurality of word lines; a plurality of bit lines which are provided in a direction intersecting the plurality of word lines; a plurality of memory cells which are arranged in a matrix pattern that corresponds to intersections between the plurality of word lines and the plurality of bit lines; a plurality of sense amplifiers which are associated with the plurality of bit lines on a one-on-one basis; a plurality of switch circuits each of which belongs to one of first to n-th (n is an integer equal to or larger than
2) groups, and which are associated with the plurality of bit lines and with the plurality of sense amplifiers on a one-on-one basis, each switch circuit connecting its associated bit line and sense amplifier to each other when turned on; anda timing control section for controlling at least timing of the sense amplifiers and the switch circuits which, in reading stored data out of the memory cells, executes control in which the plurality of sense amplifiers are disabled while the plurality of switch circuits are turned on for a given period of time, the plurality of switch circuits are turned off and then the plurality of sense amplifiers are enabled, and, when a given period of time elapses since the relevant sense amplifiers are enabled, the switch circuits belonging to the first to n-th groups are sequentially turned on group by group at given time intervals. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An operation method of a semiconductor memory device comprising:
- a plurality of word lines;
a plurality of bit lines which are provided in a direction intersecting the plurality of word lines;
a plurality of memory cells which are arranged in a matrix pattern that corresponds to intersections between the plurality of word lines and the plurality of bit lines;
a plurality of sense amplifiers which are associated with the plurality of bit lines on a one-on-one basis; and
a plurality of switch circuits which, when turned on, connect the plurality of bit lines and the plurality of sense amplifiers to each other,the method comprising; disabling the plurality of sense amplifiers while turning on the plurality of switch circuits for a given period of time; turning off the plurality of switch circuits and then enabling the plurality of sense amplifiers; and when a given period of time elapses since the sense amplifiers are enabled, dividing the plurality of switch circuits into a plurality of groups so that the switch circuits are sequentially turned on group by group at given time intervals. - View Dependent Claims (9)
- a plurality of word lines;
Specification