Wireless Communication Network Analyzer

• US 20100110916A1
• Filed: 06/23/2009
• Published: 05/06/2010
• Est. Priority Date: 06/23/2008
• Status: Active Grant

• Current Assignee: FieldComm Group, Inc.
• Original Assignee: Hart Communication Foundation (FieldComm Group, Inc.)
• Inventors: Okamura, Mark M., Middleton, Chuck, Hathiram, Daraius, Pratt, Wallace A. JR., Ham, Ronald E.
• Granted Patent: US 8,441,947 B2
• Time in Patent Office: Days
• US Class Current: 370/252
• CPC Class Codes: H04L 43/50 Testing arrangements
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements

Abstract

A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels includes a plurality of inputs to receive a respective plurality of signals, such that each of the plurality of signals is indicative of a presence of a data packet on a respective one of the plurality of communication channels, a clock source to supply a periodic clock signal, a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of signals, such that each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process the respective signal independently of every other one of the plurality of processing modules, and an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels.

Claims

1. A packet controller for simultaneous processing of data packets transmitted via a plurality of communication channels, the packet controller comprising:

a plurality of inputs to receive a respective plurality of signals, wherein each of the plurality of signals is indicative of a presence of a data packet on a respective one of the plurality of communication channels;

a clock source to supply a periodic clock signal;

a plurality of independent processing modules coupled to the respective plurality of inputs to simultaneously process the plurality of signals, wherein each of the plurality of independent processing modules implements a respective state machine driven by the periodic clock signal to process the respective signal independently of every other one of the plurality of processing modules; and

an output to transmit an output signal indicative of a presence of at least one data packet on one or more of the plurality of communication channels.

2. The packet controller of claim 1, further comprising a counter communicatively coupled to each of the plurality of independent processing modules and to the clock source to count a number of clock cycles of the periodic clock signal that have occurred since a reference time.

3. The packet controller of claim 2, wherein each of the plurality of independent processing modules uses the counter to generate a time stamp for each data packet detected on the respective one of the plurality of communication channels.

4. The packet controller of claim 1, wherein the clock source is a first clock source, and the periodic clock signal is a first periodic clock signal associated with a first clock cycle duration;

and wherein the packet controller further comprises;

a second clock source to continuously supply a second periodic clock signal associated with a second clock cycle duration shorter than the first clock cycle duration;

wherein the first periodic clock signal drives state transitions of each of the plurality of independent processing modules, and the second periodic clock is used to execute instructions in each of the plurality of independent processing modules.

5. The packet controller of claim 1, wherein the plurality of inputs is a first a plurality of inputs, and wherein the plurality of signals is a plurality of data packet start signals from a respective plurality of transceivers, each of the plurality of data packet start signals being indicative of a start of reception of the data packet by a respective one of the plurality of transceivers on the respective one of the plurality of communication channels.

6. The packet controller of claim 5, further comprising a second plurality of inputs to receive a respective plurality of data packet end signals from the respective plurality of transceivers, each of the plurality of data packet end signals being indicative of an end of reception of the data packet by the respective one of the plurality of transceivers on the respective one of the plurality of communication channels.

7. The packet controller of claim 5, further comprising:

a second plurality of inputs to receive a respective plurality of data packet signals from the respective plurality of transceivers, each of the plurality of data packet signals conveying the data packet received by the respective one of the plurality of transceivers on the respective one of the plurality of communication channels;

a multiplexer coupled to the plurality of independent processing modules; and

an output coupled to the multiplexer to transmit data packets received on the plurality of communication channels.

8. The packet controller of claim 5, further comprising:

a master serial parallel interface (SPI) coupled to exchange data with a processor, the master SPI including;

a master output, slave input (MOSI) to receive transceiver control data from the processor;

a master input, slave output (MISO) to transmit data packets to the processor; and

a serial clock input (SCLK) to receive a master clock signal from the processor; and

a plurality of slave SPIs coupled to the respective plurality of transceivers, each one of the plurality of SPIs including;

a MISO to receive the data packets from a respective one of the plurality of transceivers; and

a MOSI to forward the transceiver control data to the respective one of the plurality of transceivers; and

a serial clock input (SCLK) to forward the master clock signal to the respective one of the plurality of transceivers.

9. The packet controller of claim 5, further comprising a mode selection input to receive a selection signal from a processor to select between at least a receive mode and a control mode of operation of the packet controller;

wherein the receive mode corresponds to receiving data packets from the plurality of plurality of transceivers and forwarding the received data packets to the processor, and the control mode corresponds to receiving control data from the processor and forwarding the received control data to a specified one of the plurality of transceivers.

10. The packet controller of claim 1, wherein the plurality of signals is a plurality of signals from a plurality of transceivers, each associated with a respective one of the plurality of communication channels;

the packet controller further comprising;

a control data input to receive control data for the plurality of transceivers; and

a selection input to receive a selection of one of the plurality of transceivers;

wherein the packet controller forwards the control data to the selected one of the plurality of transceivers.

11. A method of monitoring data packets on a communication link having a plurality of wireless communication channels, the method comprising:

simultaneously capturing a plurality of wireless signals, each associated with a respective one of the plurality of wireless communication channels, to generate a respective plurality of electronic signals;

processing the plurality of electronic signals in parallel, including;

obtaining a periodic clock signal;

simultaneously driving a plurality of state machines using the periodic clock signal to retrieve data packets transmitted via the plurality of wireless communication channels, wherein each of the plurality of state machines corresponds to a respective one of the plurality of wireless communication channels and uses a respective one of the plurality of electronic signals; and

generating a data stream including the retrieved data packets for subsequent processing.

12. The method of claim 11, wherein simultaneously capturing the plurality of wireless signals includes:

capturing a wireless signal that includes the plurality of wireless signals using a single antenna;

splitting the captured wireless signal into a plurality of copies of the captured wireless signal; and

supplying the plurality of copies of the captured wireless signal to a plurality of wireless transceivers to generate the multiplicity of electronic signals.

13. The method of claim 12, further comprising amplifying the captured wireless signal prior to splitting the captured wireless signal.

14. The method of claim 12, wherein each of the plurality of wireless transceivers is tuned to a frequency associated with a corresponding one of the plurality of communication channels.

15. The method of claim 12, wherein each of the plurality of wireless transceivers generates, for a corresponding one of the plurality of communication channels a packet start signal indicative of a beginning of a data packet, and a packet end signal indicative of an end of a data packet.

16. The method of claim 11, wherein processing the plurality of channel-specific signals in parallel further includes generating a time stamp for each captured data packet, including generating an equal time stamp for two data packets captured at two distinct wireless communication channels within a same cycle of the periodic clock signal.

17. The method of claim 11, wherein processing the plurality of electronic signals in parallel further includes maintaining an independent first-in-first-out (FIFO) memory buffer for each of the plurality of electronic signals.

18. The method of claim 11, further comprising:

transmitting the data stream to a user interface executing on a computer system; and

displaying the data stream at the user interface.

19. A radio interface circuit for use in a wireless communication network analyzer that simultaneously captures communications on a plurality of RF carriers, the radio interface circuit comprising:

an RF input to receive a signal associated with the plurality of RF carriers from an antenna;

a splitting module communicatively coupled to the RF input to split the received signal into a plurality of signals;

wherein the splitting module includes a plurality of outputs at which the splitting module outputs the respective plurality of signals;

a plurality of radio transceivers, each coupled to a respective one of the plurality of outputs to process the plurality of signals in parallel and generate a respective plurality of data streams; and

a processing unit communicatively coupled to the plurality of radio transceivers to process data associated with the plurality of data streams.

20. The radio interface circuit of claim 19, further comprising an amplifier disposed downstream of the RF input and upstream of the splitting module to amplify the received signal prior to splitting the received signal at the splitter.

21. The radio interface circuit of claim 19, wherein the splitting module includes:

a first-stage splitter having an input coupled to the RF input, and a multiplicity of outputs; and

a multiplicity of second-stage splitters, each having an input coupled to a respective one of the multiplicity of outputs of the first-stage splitter, and a plurality of outputs;

wherein the pluralities of outputs of the multiplicity of second-stage splitters define the plurality of outputs of the splitting module.

22. The radio interface circuit of claim 21, wherein the splitting module further includes a multiplicity of second-stage amplifiers, each disposed between a respective one of the multiplicity of outputs and a respective one of the multiplicity of second-stage splitters.

23. The radio interface circuit of claim 19, further comprising a packet controller coupled to the

24. The radio interface circuit of claim 19, further comprising a clock source to generate a clock signal and provide the clock signal to each of the plurality of radio transceivers.

25. The radio interface circuit of claim 19, further comprising a packet controller including:

a plurality of inputs, each coupled to a respective one of the plurality of radio transceivers;

a clock source to supply a periodic clock signal;

a plurality of independent state machines, each driven by the periodic clock signal and coupled to a respective one of the plurality of inputs to simultaneously process a respective one of the plurality of data streams; and

a multiplexer coupled to the plurality of independent state machines to provide an output data stream that includes data packets from the plurality of data streams;

wherein the output data stream is provided to the processing unit.