VIDEO PROCESSING APPARATUS AND METHODS

• US 20100111181A1
• Filed: 11/06/2008
• Published: 05/06/2010
• Est. Priority Date: 11/06/2008
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, To-Wei, Chang, Te-Hao
• Application Number:
  US12/265,796
• Publication Number:
  US 20100111181A1
• Time in Patent Office: Days
• US Class Current: 375/240.160
• CPC Class Codes: H04N 19/433 characterised by techniques for memory access
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/85 using pre-processing or post-processing specially adapted for video compression

Abstract

A video processing apparatus includes a video decoder and a post-processing device. The video decoder is provided for decoding a block-based compressed bitstream to generate a sequence of frames, wherein data of reference frames in the sequence of frames are provided for generating a current frame. The post-processing device couples to a first memory and the video decoder. The video decoder sequentially stores the sequence of frames on a block-by-block basis and in a decoding order into the first memory. The post-processing device acquires the sequence of frames block by block, extracts motion information, and performs post-processing according to the sequence of frames and the motion information.

Claims

1. A video processing apparatus, comprising:

a video decoder for generating a sequence of frames by decoding a block-based compressed bitstream, wherein data of reference frames in the sequence of frames are provided for generating a current frame;

a first memory sequentially storing the sequence of frames output from the video decoder on a block-by-block basis and in a decoding order; and

a post-processing device coupled to the video decoder and the first memory, comprising a motion estimation unit, acquires the sequence of frames block by block from the first memory, extracts motion information from the sequence of frames for post-processing.

2. The video processing apparatus as claimed in claim 1, wherein the addressing mode of the first memory is block-based.

3. The video processing apparatus as claimed in claim 1, wherein the video decoder further derives motion vectors and side information associated with the sequence of frames for the post-processing device.

4. The video processing apparatus as claimed in claim 3, wherein the post-processing device comprises:

a motion compensation unit coupled to the first memory and the motion estimation unit for generating post-processed video in accordance with the motion information from the motion estimation unit.

5. The video processing apparatus as claimed in claim 4, wherein the motion compensation unit generates the post-processed video in accordance with the motion vectors and the side information from the video decoder.

6. The video processing apparatus as claimed in claim 3, wherein the side information comprises block mode information, DC coefficients, AC coefficients, directional transform information and quantization parameters.

7. The video processing apparatus as claimed in claim 1, wherein the video decoder acquires the data of reference frames from the first memory to generate the current frame.

8. The video processing apparatus as claimed in claim 1, wherein the video decoder comprises:

a second memory for storing the data of reference frames on a block-by-block basis and in the decoding order output from the video decoder,

wherein the video decoder acquires the data of reference frames from the second memory to generate the current frame.

9. The video processing apparatus as claimed in claim 1, wherein the motion estimation unit retrieves two frames from the sequence of frames in a predetermined order, extracting motion information associated with the two frames, and the post-processing device further comprises a motion compensation unit for generating an interpolated frame between the two frames according to the motion information extracted by the motion estimation unit.

10. The video processing apparatus as claimed in claim 9, wherein the interpolated frame is generated by performing motion judder cancellation processing on the two frames.

11. The video processing apparatus as claimed in claim 10, wherein the predetermined order is determined in accordance with motion judder cancellation.

12. The video processing apparatus as claimed in claim 9, wherein the two frames are successive frames.

13. A video processing method, comprising:

receiving a block-based compressed bitstream;

decoding the block-based compressed bitstream to generate a sequence of frames by a video decoder, wherein data of reference frames in the sequence of frames are provided for generating a current frame;

sequentially storing the sequence of frames output from the video decoder into a first memory on a block-by-block basis and in a decoding order;

acquiring the sequence of frames block by block from the first memory to extract motion information from the sequence of frames; and

performing post-processing on the sequence of frames based on the motion information.

14. The video processing method as claimed in claim 13, wherein the addressing mode of the first memory is block-based.

15. The video processing method as claimed in claim 13, wherein the step of decoding the sequence of frames comprises:

deriving motion vectors and side information associated with the sequence of frames.

16. The video processing method as claimed in claim 13, wherein the step of performing post-processing comprises:

retrieving two frames from the sequence of frames in a predetermined order;

extracting motion information associated with the two frames; and

generating an interpolated frame between the two frames in accordance with the motion information, the motion vectors and the side information.

17. The video processing method as claimed in claim 16, wherein the interpolated frame is generated by performing motion judder cancellation on the two frames.

18. The video processing method as claimed in claim 16, wherein the predetermined order is determined in accordance with motion judder cancellation.

19. The video processing method as claimed in claim 15, wherein the side information comprises block mode information, DC coefficients, AC coefficients, directional transform information and quantization parameters.

20. The video processing method as claimed in claim 13, wherein the reference frames are acquired from the first memory to generate the current frame.

21. The video processing method as claimed in claim 13, further comprising:

providing a second memory for storing the data of reference frames output from the video decoder on the block-by-block basis and in the decoding order; and

acquiring the data of reference frames from the second memory to generate the current frame,

wherein the addressing mode of the second memory is block-based.