SEMICONDUCTOR MEMORY DEVICE

• US 20100112753A1
• Filed: 11/13/2009
• Published: 05/06/2010
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,867,822 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0104 Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method includes forming a switching device which includes a vertical channel spaced apart from a semiconductor substrate, and forming a storage device which is positioned on opposed sides of the switching device. The storage device includes a cylindrically shaped storage node, a plate electrode coupled to the storage node, and a dielectric film which is formed between the storage node and plate electrode, the storage nodes being electrically connected to the switching device.

Claims

1. A method, comprising:

forming a switching device which includes a vertical channel spaced apart from a semiconductor substrate; and

forming a storage device which is positioned on opposed sides of the switching device, wherein the storage device includes a cylindrically shaped storage node, a plate electrode coupled to the storage node, and a dielectric film which is formed between the storage node and plate electrode, the storage nodes being electrically connected to the switching device.

2. The method of claim 1, wherein the step of forming the switching device includes forming a mesa structure.

3. The method of claim 2, wherein the step of forming the switching device includes forming a gate electrode which extends around the mesa structure.

4. The method of claim 3, wherein the step of forming the switching device includes forming a dielectric film which extends around the mesa structure.

5. The method of claim 3, wherein the step of forming the switching device includes forming single crystalline semiconductor.

6. A method for fabricating three-dimensional semiconductor device, comprising:

providing a first semiconductor substrate;

forming a lower semiconductor device on the first semiconductor substrate;

forming a interlayer dielectric film which covers the lower semiconductor device;

bonding a second semiconductor substrate to the interlayer dielectric film, wherein the second semiconductor substrate includes multiple doped layers;

patterning the multiple doped layers to form vertically structured semiconductor devices on the interlayer dielectric film.

7. The method of claim 6, wherein forming vertically structured semiconductor devices is to form vertical transistors which have vertical channels to the first semiconductor substrate.

8. The method of claim 7, wherein the multiple doped layers are patterned to form channel regions and source/drain regions of the transistors.

9. The method of claim 6, wherein a bonding layer is formed on the interlayer dielectric film before bonding the second semiconductor substrate.

10. The method of claim 9, wherein the bonding layer is formed with dielectric or conducting material.

11. A method for fabricating three-dimensional semiconductor device, comprising:

providing a first semiconductor substrate which includes chip areas including lower semiconductor devices and alignment areas including alignment keys;

bonding a second semiconductor substrate on the first semiconductor substrate;

removing parts of the second semiconductor substrate which is located on the alignment areas of the first semiconductor substrate;

forming upper semiconductor devices on other area of the second semiconductor substrate located on the chip areas of the first semiconductor substrate;

wherein the other area of the second semiconductor substrate is remaining area of the second semiconductor substrate excluding the removed parts of the second semiconductor substrate.

12. The method of claim 11, wherein the first and second semiconductor substrates include flat zone or notch in the circumference of the substrate.

13. The method of claim 12, wherein the bonding is performed by aligning the flat zone or notch of the first and second semiconductor substrates.

14. The method of claim 12, wherein the alignment area is located in between chip areas.

15. The method of claim 11, wherein:

providing the first semiconductor substrate includes forming the lower semiconductor devices on the chip area of the first semiconductor substrate and the alignment keys on the alignment areas;

forming interlayer dielectric films which covers the lower semiconductor devices;

forming interconnects in the interlayer dielectric films which are electrically connected to the lower semiconductor substrate.

16. The method of claim 15, wherein in a bonding layer is formed on the interlayer dielectric films before bonding the second semiconductor substrate.