Resistive random access memory and method for manufacturing the same

• US 20100112810A1
• Filed: 01/05/2010
• Published: 05/06/2010
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lai, Erh-Kun, Hsieh, Kuang-Yeu, Ho, Chia-Hua, Lee, Ming-Daou
• Granted Patent: US 8,114,715 B2
• Time in Patent Office: Days
• US Class Current: 438/666
• CPC Class Codes: H10N 70/028 by conversion of electrode material, e.g. oxidation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/828 Current flow limiting means within the switching material region, e.g. constrictions
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

Claims

1. A manufacturing method of resistive random access memory, comprising:

(a) forming an insulating layer, wherein the insulating layer has a contact hole having a first width;

(b) forming a spacer in the contact hole, wherein the spacer has a first opening having a second width smaller than the first width;

(c) forming a memory cell having the second width; and

(d) forming a top electrode coupled with the memory cell.

2. The manufacturing method according to claim 1, further comprising forming an anti-oxidation barrier material , wherein the insulating layer is formed on the anti-oxidation barrier material.

3. The manufacturing method according to claim 2, further comprising etching the anti-oxidation barrier material so as to form an anti-oxidation barrier having a second opening, wherein the second opening has the second width.

4. The manufacturing method according to claim 3, further comprising removing the spacer.

5. The manufacturing method according to claim 1, wherein between step (a) and step (b), the method further comprises

forming a conductive layer in the contact hole;

planarizing the conductive layer to expose the insulating layer; and

etching the conductive layer for creating a distance between the surface of the conductive layer and the surface of the insulating layer.

6. The manufacturing method according to claim 5 further comprising oxidizing the conductive layer prior to step (b).

7. The manufacturing method according to claim 5, wherein the step (d) further comprises oxidizing the conductive layer

8. The manufacturing method according to claim 1, further comprising

forming a bottom electrode, wherein the insulating layer is formed on.

9. The manufacturing method according to claim 8, further comprising oxidizing the bottom electrode prior to the step (b).

10. The manufacturing method according to claim 8, wherein the step (c) further comprises oxidizing the bottom electrode so as to form an oxide layer.

11. A manufacturing method of memory device, comprising:

forming an insulating layer;

etching the insulating layer to form a hole;

forming a first electrode and a memory layer in the hole;

forming a spacer in the hole and over the memory layer; and

forming a second electrode over the spacer and in contact with the memory layer, the second electrode having first and second widths, wherein the first width is larger than the second width.