DEVICE AND METHOD FOR TESTING A CIRCUIT

• US 20100114508A1
• Filed: 11/30/2006
• Published: 05/06/2010
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Parnes, Erez, Arbel-Meirovich, Erez, Alankry, Yaron, Glickman, Eran
• Granted Patent: US 8,452,553 B2
• Time in Patent Office: Days
• US Class Current: 702/58
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.

Claims

1. A device, the device comprises:

a processor;

an interface adapted to receive a test vector and to output a test response, wherein the test vector comprises a first group of signals that comprises idle signals and at least one information frame and a second group of signals that comprises timing signals and data signals;

a receiver, coupled to the interface, wherein the receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction;

wherein the processor, is coupled to the receiver;

wherein the device is adapted to send the at least one instruction to at least one instruction buffer;

wherein the processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide a test response.

2. The device according to claim 1 wherein the device comprises multiple data buffers and wherein the data buffers are adapted to store multiple data signals of the second group of signals.

3. The device according to claim 1 wherein the processor is adapted to send the at least one instruction to at least one instruction buffer in response to an instruction type identifier associated with the instruction.

4. The device according to claim 1 wherein the interface comprises at least one pin adapted to receive only signals that belong to the first group of signals.

5. The device according to claim 1 wherein the interface comprises at least one pin adapted to receive signals that belong to the first group of signals and to the second group of signals.

20. The device according to claim 2 wherein the processor is adapted to send the at least one instruction to at least one instruction buffer in response to an instruction type identifier associated with the instruction.

6. A tester that comprises:

a pattern generator adapted to generate a second group of signals that comprises timing signals and data signals;

an interface adapted to receive information representative of at least one instruction; and

a controller adapted to control a provision of a test vector to a tested test;

wherein the test vector comprises the second group of signals and a first group of signals that comprises idle signals and at least one information frame;

wherein the controller is adapted to evaluate a test response received from the tested device in response to the test vector provided to the tested device.

7. The tester according to claim 6 wherein the tester provides only signals that belong to the first group of signals to a pin of the tested device.

8. The tester according to claim 6 wherein the tester provides signals that belong to the first group of signals and to the second group of signals to a pin of the tested device.

9. A method for testing a device, the method comprises:

outputting a test response;

receiving a test vector, wherein the test vector comprises a first group of signals that comprises idle signals and at least one information frame and a second group of signals that comprises timing signals and data signals;

filtering out, by a receiver, idle signals and at least one instruction delimiters to provide at least one instruction;

sending the at least one instruction to at least one instruction buffer; and

generating a test response by executing the at least one instruction and by responding to the second group of signals.

10. The method according to claim 9 wherein the method comprises sending multiple data signals of the test vector to multiple data buffers.

11. The method according to claim 9 wherein a size of a single instruction frame does not exceed one percent of the test vector.

12. The method according to claim 9 wherein the sending is responsive to an instruction type identifier associated with the instruction.

13. The method according to claim 9 wherein receiving comprises receiving, via at least one pin of the tested device, only signals that belong to the first group of signals.

14. The method according to claim 9 wherein receiving comprises receiving, via at least one pin of the tested device, signals that belong to the first group of signals and to the second group of signals.

19. The method according to claim 10 wherein a size of a single instruction frame does not exceed one percent of the test vector.

15. A method for testing a tested device, the method comprises:

generating a second group of signals that comprises timing signals and data signals;

receiving information representative of at least one instruction;

generating a test vector that comprises the second group of signals and a first group of signals that comprises idle signals and at least one information frame, wherein the first group of signals is responsive to the information representative of at least one instruction;

providing the test vector to the tested device; and

evaluating a test response received from the tested device in response to the provision of the test vector.

16. The method according to claim 15 wherein the providing comprises providing only signals that belong to the first group of signals to a pin of the tested device.

17. The method according to claim 15 wherein the providing comprises providing signals that belong to the first group of signals and to the second group of signals to a pin of the tested device.

18. The method according to claim 16 wherein the providing comprises providing signals that belong to the first group of signals and to the second group of signals to a pin of the tested device.