BRIDGE DEVICE HAVING A VIRTUAL PAGE BUFFER

• US 20100115172A1
• Filed: 10/28/2009
• Published: 05/06/2010
• Est. Priority Date: 11/04/2008
• Status: Abandoned Application

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: GILLINGHAM, Peter B., PYEON, Hong Beom, KIM, Jin-Ki
• Application Number:
  US12/607,680
• Publication Number:
  US 20100115172A1
• Time in Patent Office: Days
• US Class Current: 710/310
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has a virtual page buffer corresponding to each discrete memory device for storing read data from the discrete memory device, or write data from an external device. The virtual page buffer is configurable to have a size up to the maximum physical size of the page buffer of a discrete memory device. The page buffer is then logically divided into page segments, where each page segment corresponds in size to the configured virtual page buffer size. By storing read or write data in the virtual page buffer, both the discrete memory device and the external device can operate to provide or receive data at different data rates to maximize the performance of both devices.

Claims

1. A bridge device, comprising:

a virtual page buffer for storing data;

a bridge device interface for transferring data between an external device and the virtual page buffer at a first data rate in response to a global command; and

,

a memory device interface for transferring data between a memory device and the virtual page buffer at a second data rate in response to a local command.

2. The bridge device of claim 1, wherein the memory device includes a page buffer having a fixed maximum size.

3. The bridge device of claim 2, wherein the virtual page buffer is configurable to have a size equal to the fixed maximum size of the page buffer.

4. The bridge device of claim 2, wherein the virtual page buffer is configured to have a size corresponding to a page segment of the page buffer.

5. The bridge device of claim 4, wherein the memory device interface transfers the data corresponding to the page segment between the memory device and the virtual page buffer.

6. The bridge device of claim 4, wherein the global command includes a virtual page address for selecting the page segment of the page buffer.

7. The bridge device of claim 6, wherein the page segment is one of 2ⁿ page segments and the virtual page address is an n-bit address, where n is an integer number of at least 1.

8. The bridge device of claim 6, wherein the global command includes a virtual column address for selecting a bit of the page segment.

9. The bridge device of claim 6, further including a converter circuit for converting the virtual page address into a physical address corresponding to the page segment.

10. The bridge device of claim 9, wherein the converter circuit generates the local command to include the physical address in a format compatible with the memory device.

11. The bridge device of claim 3, wherein the memory device is a first memory device, the virtual page buffer is a first virtual page buffer, and the memory interface is coupled to a second memory device for transferring data between the second memory device and a second virtual page buffer.

12. The bridge device of claim 11, further including a virtual page size configuration circuit for configuring the size of the first virtual page buffer and the second virtual page buffer in response to a virtual page size configuration command.

13. The bridge device of claim 12, wherein the virtual page size configuration command includes an op-code field followed by a first virtual page size data field containing a first configuration code corresponding to the first virtual page buffer, and a second virtual page size data field containing a second configuration code corresponding to the second virtual page buffer.

14. The bridge device of claim 1, wherein the first data rate is greater than the second data rate.

15. The bridge device of claim 1, further including data path circuits for transferring data between the bridge device interface and the virtual page buffer at the first data rate.

16. The bridge device of claim 15, wherein the data path circuits includes a data input path circuit for transferring write data received at the bridge device interface to the virtual page buffer for storage in the virtual page buffer, and a data output path circuit for transferring read data stored in the virtual page buffer to the bridge device interface.

17. The bridge device of claim 16, wherein the virtual page buffer includes a memory having

a first input port for receiving the write data from the data input path circuit,

a first output port for providing the read data to the data output path circuit,

a second input port for receiving the read from the memory device interface, and

a second output port for providing the write data stored in the memory.

18. The bridge device of claim 17, further including a converter circuit for receiving the write data from the second output port of the memory and generating the local command to transfer the write data to the memory device.

19. The bridge device of claim 1, wherein the memory device interface is asynchronous and the bridge device interface is a synchronous interface receiving a clock signal.

20. The bridge device of claim 1, wherein the memory device interface provides the local command in a parallel format, and the bridge device interface receives the global command in a serial format.

21. A bridge device, comprising:

a memory device interface for receiving read data at a first data rate;

a virtual page buffer for storing the read data received by the memory device interface; and

,

a bridge device interface for outputting the read data stored in the memory device interface at a second data rate.

22. A bridge device, comprising:

a bridge device input/output interface for receiving write data at first data rate;

a virtual page buffer for storing the write data received by the bridge device interface; and

,

a memory device interface for outputting the write data stored in the virtual page buffer at a second data rate.

23. A method for accessing read data from a discrete memory device with a bridge device, comprising:

providing a read address corresponding to the read data to the discrete memory device;

receiving the read data from the discrete memory device;

storing the read data in a virtual page buffer of the bridge device; and

,

outputting the read data stored in the virtual page buffer.

24. The method of claim 23, wherein providing includes receiving a global page read command having the read address.

25. The method of claim 24, wherein receiving the global page read command includes issuing a local page read command when the read address corresponds to a new physical page.

26. The method of claim 25, wherein issuing includes execution of a core read operation by the discrete memory device in response to the local page read command to access the read data from the new physical page.

27. The method of claim 26, wherein receiving the read data includes issuing a local burst data read command to the discrete memory device after a core read time for reading the new physical page of the discrete memory device has elapsed.

28. The method of claim 24, wherein receiving the global page read command includes issuing a local burst data read command to the discrete memory device when the read address corresponds to a previously accessed physical page.

29. The method of claim 23, wherein the read address includes a virtual page address corresponding to a page segment of a physical page of the discrete memory device.

30. The method of claim 29, wherein the page segment is one of 2ⁿ page segments and the virtual page address is an n-bit address for selecting the page segment, where n is an integer number of at least 1.

31. The method of claim 30, wherein the read address includes a virtual column address for selecting a bit of the page segment.

32. The method of claim 31, wherein providing the read address includes converting the virtual page address and the virtual column address into a physical address corresponding to the page segment.

33. A method for writing data to a discrete memory device with a bridge device, comprising:

receiving a global page program command;

storing write data to a virtual page buffer of the bridge device;

transferring the write data stored in the virtual page buffer to a discrete memory device; and

,

issuing a local program command to the discrete memory device.