MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE

• US 20100115179A1
• Filed: 10/30/2008
• Published: 05/06/2010
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Wames, Lidia, Vu, Dan, Carr, Dennis, Calhoun, Michael Bozich, Lee, Teddy
• Granted Patent: US 8,018,753 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module.

Claims

1. A memory apparatus comprising:

a memory module connector comprising;

a first plurality of pins coupled to circuitry on a memory module; and

a second plurality of pins coupled to power rails on the memory module and enabling monitoring of the power rails from external to the memory module.

2. The apparatus according to claim 1 further comprising:

the second plurality of pins comprising voltage sense lines that route signals from the power rails on the memory module for use in power sensing external to the memory module.

3. The apparatus according to claim 1 further comprising:

a memory module comprising;

the memory module connector;

a circuit board coupled to the memory module connector; and

a plurality of integrated circuits mounted to the circuit board and comprising at least one memory integrated circuit.

4. The apparatus according to claim 1 further comprising:

a plurality of memory modules, ones of the memory module plurality comprising the memory module connector, a circuit board coupled to the memory module connector, and a plurality of integrated circuits mounted to the circuit board; and

a circuit that combines power signals from the power rails of the plurality of memory modules.

5. The apparatus according to claim 1 further comprising:

a plurality of memory modules, ones of the memory module plurality comprising the memory module connector, a circuit board coupled to the memory module connector, and a plurality of integrated circuits mounted to the circuit board; and

a circuit that monitors at least one power signal from the power rails of the plurality of memory modules.

6. The apparatus according to claim 1 further comprising:

a memory module comprising;

the memory module connector;

a circuit board coupled to the memory module connector;

a plurality of memory integrated circuits mounted to the circuit board;

a voltage measurement circuit coupled to the circuit board that measures voltage on the memory module;

a register coupled to the voltage measurement circuit that holds a value representing the measured voltage on the memory module; and

a bus interface coupled to the register and coupled to the second plurality of pins.

7. The apparatus according to claim 6 further comprising:

the memory module comprising a dual in-line memory module (DIMM) with a plurality of dynamic random access memory (DRAM) integrated circuits mounted thereon;

the bus interface comprising an inter-integrated circuit (I²C) multi-master serial computer bus or a system management bus (SMBus);

an electrically-erasable programmable read-only memory (EEPROM) that supports serial presence detect (SPD) wherein SPD memory space is allocated to include the measured memory module voltage; and

a logic that reads measured memory module voltage from the serial presence detect (SPD) memory and performs dynamic power system adjustment based on the measured memory module voltage.

8. A memory apparatus comprising:

a memory module comprising;

a circuit board;

a voltage measurement circuit coupled to the circuit board that measures voltage on the memory module;

a register coupled to the voltage measurement circuit that holds a value representing the measured voltage on the memory module; and

a bus interface coupled to the register.

9. The apparatus according to claim 8 further comprising:

the memory module further comprising;

a memory module connector comprising;

a first plurality of pins coupled to circuitry on a memory module; and

a second plurality of pins coupled to the bus interface and coupled to power rails on the memory module, the second plurality of pins and the bus interface enabling monitoring of the power rails from external to the memory module.

10. The apparatus according to claim 8 further comprising:

a plurality of memory modules; and

a circuit that combines power signals from the power rails of the plurality of memory modules.

11. The apparatus according to claim 8 further comprising:

the memory module comprising a dual in-line memory module (DIMM) with a plurality of dynamic random access memory (DRAM) integrated circuits mounted thereon;

the bus interface comprising an inter-integrated circuit (I²C) multi-master serial computer bus or a system management bus (SM Bus);

an electrically-erasable programmable read-only memory (EEPROM) that supports serial presence detect (SPD) wherein SPD memory space is allocated to include the measured memory module voltage; and

a logic that reads measured memory module voltage from the serial presence detect (SPD) memory and performs dynamic power system adjustment based on the measured memory module voltage.

12. A method for managing power in a computer memory comprising:

sensing power at power rails on a memory module; and

routing signals indicative of the sensed power from the power rails of the memory module to a monitoring location external to the memory module.

13. The method according to claim 12 further comprising:

measuring voltage on the memory module at a position adjacent to a memory integrated circuit mounted to the memory module;

communicating the measured voltage to the location external to the memory module; and

adjusting operation of system components at the location external to the memory module based on the measured voltage.

14. The method according to claim 12 further comprising:

routing signals indicative of the sensed power from the power rails of a plurality of memory modules to a monitoring location external to the memory module; and

combining power signals from the power rails of the plurality of memory modules.

15. The method according to claim 12 further comprising:

measuring voltage on the memory module at a position adjacent to a memory integrated circuit mounted to the memory module;

loading a value representing the measured voltage into a register on the memory module;

enabling access to the register via a bus interface on the memory module;

accessing the register from a location external to the memory module; and

performing dynamic power system adjustment based on the measured memory module voltage.