System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices

• US 20100115191A1
• Filed: 03/19/2008
• Published: 05/06/2010
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Hampel, Craig
• Granted Patent: US 9,195,602 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 : Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1003 : Interface circuits for daisy chain or ring bus memory arrangements
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.

Claims

1. A memory system comprising:

a memory controller;

a first set of volatile memory devices defining a first memory hierarchy, the first set of volatile memory devices disposed on at least one first memory module, the at least one first memory module coupled to the memory controller in a daisy-chained configuration and including a first integrated circuit buffer device;

a second set of nonvolatile memory devices defining a second memory hierarchy, the second set of nonvolatile memory devices disposed on at least one second memory module, the at least one second memory module coupled to the at least one first memory module in a daisy-chained configuration and including a second integrated circuit buffer device.

2. The memory system of claim 1:

wherein signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.

3. The memory system of claim 1 wherein the at least one first memory module comprises a plurality of first memory modules, each of the plurality of first memory modules including respective first integrated circuit buffer devices, and wherein the respective first integrated circuit buffer devices are coupled in a daisy-chained fashion via respective sets of point-to-point links.

4. The memory system of claim 3, wherein the respective sets of point-to-point links comprise at least one upstream signal path for transmitting signals towards the memory controller, and at least one downstream signal path for transmitting signals away from the memory controller.

5. The memory system of claim 4 wherein each point-to-point link comprises a unidirectional serial link.

6. The memory system of claim 1 wherein the volatile memory devices comprise dynamic random access memory (DRAM) devices.

7. The memory system of claim 1 wherein the nonvolatile memory devices comprise flash memory devices.

8. The memory system of claim 1 wherein the at least one first memory module comprises a fully buffered dual inline memory module.

9. The memory system of claim 1 wherein the at least one second memory module comprises a plurality of second memory modules, each of the plurality of second memory modules including respective second integrated circuit buffer devices, and wherein the respective second integrated circuit buffer devices are coupled in a daisy-chained fashion to each other via respective sets of point-to-point links.

10. The memory system of claim 9, wherein the respective sets of point-to-point links comprise at least one upstream signal path for transmitting signals towards the memory controller, and at least one downstream signal path for transmitting signals away from the memory controller.

11. The memory system of claim 10 wherein each point-to-point link comprises a unidirectional serial link.

12. A method of operating a memory system, the memory system having a memory controller coupled in a daisy-chained fashion to a first set of volatile memory devices disposed on at least one first memory module, the memory system including a second set of nonvolatile memory devices disposed on at least one second memory module daisy-chained to the at least one first memory module, the method comprising:

transmitting write data from the memory controller to a portion of the first set of volatile memory devices along a downstream signal path;

accumulating the write data in a portion of the first set of volatile memory devices; and

transferring the write data from the first set of volatile memory devices to a portion of the second set of nonvolatile memory devices along a second downstream signal path.

13. The method of claim 12 wherein at least two of the transmitting, accumulating and transferring operations occur concurrently.

14. The method of claim 12, wherein the volatile memory devices comprise dynamic random access memory devices, the nonvolatile memory devices comprise flash memory devices, and

wherein accumulating the write data comprises writing the write data to a parallel set of DRAM devices at like addresses;

and

wherein transferring the write data from the first set of volatile memory devices to the second set of nonvolatile devices comprises remapping the write data from the parallel set of like addresses in the first set of dynamic random access memory devices to a block in the one of the flash memory devices.

15. A method of operating a memory system, the memory system having a memory controller coupled in a daisy-chained fashion to a first set of volatile memory devices disposed on at least one first memory module, the memory system including a second set of nonvolatile memory devices disposed on at least one second memory module daisy-chained to the at least one first memory module, the method comprising:

transferring read data from a portion of the second set of nonvolatile memory devices along an upstream data path to the first set of volatile memory devices;

storing the read data in a portion of the first set of volatile memory devices;

accessing data stored in the portion of the first set of volatile memory devices.

16. The method of claim 15 wherein at least two of the transferring, storing and accessing operations occur concurrently.

17. A method of operating a memory system, the memory system having a memory controller coupled in a daisy-chained fashion to a first set of volatile memory devices disposed on at least one first memory module, the memory system including a second set of nonvolatile memory devices disposed on at least one second memory module daisy-chained to the at least one first memory module, the method comprising:

transferring first read data from a first portion of the second set of nonvolatile memory devices along a first upstream data path to the first set of volatile memory devices;

writing the first read data to a second portion of the first set of volatile memory devices;

identifying second data stored in a third portion of the first set of volatile memory devices; and

merging the first data with the second data by

transferring the first read data and the second data from the first and second portions of the first set of volatile memory devices along a downstream data path to the second set of nonvolatile memory devices, and writing the first and second data to a block portion of the second set of nonvolatile memory devices.