Memory Device and Memory System Including the Same

• US 20100115225A1
• Filed: 10/13/2009
• Published: 05/06/2010
• Est. Priority Date: 11/06/2008
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Eun, Heeseok, Song, Seung-Hwan, Kim, Jaehong, Kim, Yong June
• Application Number:
  US12/577,842
• Publication Number:
  US 20100115225A1
• Time in Patent Office: Days
• US Class Current: 711/172
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed.

Claims

1. A memory device comprising:

a word line; and

a plurality of memory cells connected to the word line,

wherein the plurality of memory cells forms a page, and

wherein the number of sectors configuring the page and the size of each of the sectors are changed.

2. The memory device as set forth in claim 1, wherein the number of sectors configuring the pages is reduced, when the reliability of the page is low.

3. The memory device as set forth in claim 2, wherein the reliability of the page is determined by a program/erase cycle number of the page.

4. The memory device as set forth in claim 2, wherein the reliability of the page is determined by a change number in a logic value of the page according to a change in threshold voltages of the memory cells of the page.

5. The memory device as set forth in claim 2, wherein the reliability of the page is determined by the number of times a read voltage is applied to the page in order to determine a logic state of each of the memory cells of the page.

6. The memory device as set forth in claim 2, wherein parities for the sectors stored in the page are stored in a storage capacity corresponding to the reduced number of sectors.

7. The memory device as set forth in claim 2, wherein the sectors stored in the page regroups into one or more groups, and the groups are set to new sectors.

8. The memory device as set forth in claim 7, wherein the groups have the same storage capacity one another.

9. The memory device as set forth in claim 7, wherein a coding rate of the sectors stored in the memory cells is equal to that of the new sectors.

10. The memory device as set forth in claim 1, wherein:

the memory cells store high-order data bits and low-order data bits, respectively;

the high-order data bits of the memory cells form a high-order page, and the low-order data bits of the memory cells form a low-order page; and

the number of sectors configuring the high-order and low-order pages and the size of each of the sectors are independently changed in each of the pages.

11. The memory device as set forth in claim 10, wherein the number of sectors configuring the low-order page is set to be smaller than the number of sectors configuring the high-order page, when the number of read operations required for distinguishing the high-order data bits is smaller than the number of read operations required for distinguishing the low-order data bits.

12. A memory system comprising:

a memory device; and

a controller controlling the memory device,

wherein;

the memory device includes a word line and a plurality of memory cells connected to the word line;

the plurality of memory cells forms a page; and

the number of sectors configuring the page and the size of each of the sectors are changed.

13. The memory system as set forth in claim 12, wherein the memory device and the controller configure a solid state drive (SSD).