DYNAMICALLY-SELECTABLE VECTOR REGISTER PARTITIONING

• US 20100115233A1
• Filed: 10/31/2008
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Abandoned Application

• Current Assignee: Convey Computer
• Original Assignee: Convey Computer
• Inventors: Wallach, Steven J., Brewer, Tony
• Application Number:
  US12/263,232
• Publication Number:
  US 20100115233A1
• Time in Patent Office: Days
• US Class Current: 712/7
• CPC Class Codes: G06F 15/8084 Special arrangements thereof, e.g. mask or switch
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a fixed vector register partitioning mode, embodiments of the present invention enable a processor to be dynamically set to any of a plurality of different vector partitioning modes. Thus, for instance, different vector register partitioning modes may be employed for different applications being executed by the processor, and/or different vector register partitioning modes may even be employed for use in processing different vector oriented operations within a given applications being executed by the processor, in accordance with certain embodiments of the present invention.

Claims

1. A method for processing data comprising:

analyzing structure of data to be processed; and

selecting one of a plurality of vector register partitioning modes based on said analyzing, wherein said vector register partitioning modes define how vector register elements are to be partitioned for processing said data.

2. The method of claim 1 further comprising:

dynamically setting a processor to use the selected one of the plurality of vector register partitioning modes for partitioning vector register elements of the processor.

3. The method of claim 2 wherein the processor comprises a co-processor in a multi-processor system.

4. The method of claim 2 wherein the selecting comprises:

selecting said one of the plurality of vector register partitioning modes to partition said vector register elements of the processor to optimize performance of vector processing operations by the processor.

5. The method of claim 2 wherein the processor comprises a plurality of application engines;

each of the plurality of application engines comprises a plurality of function pipes; and

each of the plurality of function pipes comprises a set of vector registers that each contain vector register elements.

6. The method of claim 5 wherein the plurality of vector register partitioning modes comprise at least:

a classic vector mode in which all vector register elements of the processor form a single partition;

a physical partition mode in which vector register elements of each of said application engines form a separate partition; and

a short vector mode in which the vector register elements of each of said function pipes form a separate partition.

7. The method of claim 1 further comprising:

dynamically setting, for a selected vector register partitioning mode, a vector stride and a vector partition stride for controlling memory access pattern when performing a vector register memory load or store.

8. A co-processor in a multi-processor system, the co-processor comprising:

at least one application engine having vector registers containing vector register elements for storing data for vector oriented operations by the at least one application engine; and

said at least one application engine being dynamically settable to any of a plurality of different vector register partitioning modes, wherein said vector register elements are partitioned according to the vector register partitioning mode to which the at least one application engine is dynamically set.

9. The co-processor of claim 8 further comprising:

a control register comprising dynamically settable information for setting a vector stride and a vector partition stride for controlling memory access pattern when performing a vector register memory load or store.

10. The co-processor of claim 8 further comprising:

said at least one application engine further comprising at least one configurable function unit that is configurable to any of a plurality of different vector processing personalities.

11. The co-processor of claim 10 further comprising:

a co-processor infrastructure common to all the plurality of different vector processing personalities.

12. The co-processor of claim 11 wherein the co-processor infrastructure comprises:

a memory management infrastructure, a system interface infrastructure for interfacing with a host processor, and an instruction decode infrastructure that are common to all the plurality of different vector processing personalities.

13. The co-processor of claim 12 wherein the co-processor infrastructure further comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different vector processing personalities.

14. The co-processor of claim 11 wherein said plurality of different vector processing personalities comprise:

a single-precision vector processing personality and a double-precision vector processing personality.

15. The co-processor of claim 8 comprising:

a plurality of said application engines;

each of the plurality of application engines comprising a plurality of function pipes; and

each of the plurality of function pipes comprising a set of vector registers containing vector register elements.

16. The co-processor of claim 15 wherein the plurality of vector register partitioning modes comprise:

a classic vector mode in which all vector register elements of the function pipes form a single partition;

a physical partition mode in which vector register elements of each of said application engines form a separate partition; and

a short vector mode in which the vector register elements of each of said function pipes form a separate partition.

17. A system for processing data comprising:

at least one application engine having at least one configurable function unit that is configurable to any of a plurality of different vector processing personalities;

an infrastructure common to all the plurality of different vector processing personalities;

vector registers containing vector register elements for storing data for vector oriented operations by the at least one application engine; and

wherein said at least one application engine is dynamically settable to any of a plurality of different vector register partitioning modes, said vector register partitioning mode to which the at least one application engine is dynamically set defining how said vector register elements are partitioned.

18. The system of claim 17 wherein said infrastructure comprises virtual memory and instruction decode infrastructure.

19. The system of claim 17 wherein the infrastructure comprises:

a memory management infrastructure, a system interface infrastructure for interfacing with a host processor, and an instruction decode infrastructure that are common to all the plurality of different vector processing personalities.

20. The system of claim 17 wherein the infrastructure further comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different vector processing personalities.

21. The system of claim 17 wherein said plurality of different vector processing personalities comprise:

a single-precision vector processing personality and a double-precision vector processing personality.

22. The system of claim 17 comprising:

a plurality of said application engines;

each of the plurality of application engines comprising a plurality of function pipes; and

each of the plurality of function pipes comprising a set of vector registers containing vector register elements.

23. The system of claim 22 wherein the plurality of vector register partitioning modes comprise:

a classic vector mode in which all vector register elements of the function pipes form a single partition;

a physical partition mode in which vector register elements of each of said application engines form a separate partition; and

a short vector mode in which the vector register elements of each of said function pipes form a separate partition.

24. A multi-processor system comprising:

a host processor; and

a co-processor, said co-processor including vector registers containing vector register elements for storing data for vector oriented operations by the co-processor;

a control register comprising dynamically settable information for dynamically setting said co-processor to any of a plurality of different vector register partitioning modes, wherein said vector register elements are partitioned according to the vector register partitioning mode to which the co-processor is dynamically set; and

said control register comprising dynamically settable information for setting at least one of a vector stride and a vector partition stride for controlling memory access pattern when said co-processor is performing a vector register memory load or store.

25. The multi-processor system of claim 24 wherein said control register comprises dynamically settable information for setting both said vector stride and vector partition stride.

26. The multi-processor system of claim 24 wherein said co-processor further comprises:

at least one configurable function unit that is configurable to any of a plurality of different vector processing personalities.

27. The multi-processor system of claim 26 where said co-processor further comprises:

a virtual memory and instruction decode infrastructure that is common to all the plurality of different vector processing personalities.

28. The multi-processor system of claim 24 wherein said co-processor comprises:

a plurality of application engines;

each of the plurality of application engines comprising a plurality of function pipes; and

each of the plurality of function pipes comprising a vector register containing vector register elements.

29. The multi-processor system of claim 28 wherein the plurality of vector register partitioning modes comprise:

a classic vector mode in which all vector register elements of the function pipes form a single partition;

a physical partition mode in which vector register elements of each of said application engines form a separate partition; and

a short vector mode in which the vector register elements of each of said function pipes form a separate partition.

30. A method comprising:

initiating an executable file for processing instructions of the executable file by a multi-processor system, wherein the multi-processor system comprises a host processor and a co-processor;

setting said co-processor to a selected one of a plurality of different vector register partitioning modes, said selected vector register partitioning mode defining how vector register elements of the co-processor are partitioned for use in performing vector oriented operations for processing a portion of the instructions of the executable file;

processing, by the multi-processor system, the instructions of the executable file, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.

31. The method of claim 30 wherein said co-processor comprises:

a plurality of application engines;

each of the plurality of application engines comprising a plurality of function pipes; and

each of the plurality of function pipes comprising a vector register containing a plurality of vector register elements; and

wherein the plurality of vector register partitioning modes comprise;

a classic vector mode in which all vector register elements of the function pipes form a single partition;

a physical partition mode in which vector register elements of each of said application engines form a separate partition; and

a short vector mode in which the vector register elements of each of said function pipes form a separate partition.

32. A method comprising:

initiating an executable file for processing instructions of the executable file by a multi-processor system, wherein the multi-processor system comprises a host processor and a co-processor;

determining one of a plurality of different vector register partitioning modes desired for the co-processor, said desired vector register partitioning mode defining how vector register elements of the co-processor are partitioned for use in performing vector oriented operations for processing a portion of the instructions of the executable file;

when determined that the co-processor is set to the desired vector register partitioning mode, dynamically setting the co-processor to the desired vector register partitioning mode; and

processing, by the multi-processor system, the instructions of the executable file, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.

33. The method of claim 32 wherein said co-processor comprises:

a plurality of application engines;

each of the plurality of application engines comprising a plurality of function pipes; and

each of the plurality of function pipes comprising a vector register containing vector register elements; and

wherein the plurality of vector register partitioning modes comprise;

a classic vector mode in which all vector register elements of the function pipes form a single partition;

a physical partition mode in which vector register elements of each of said application engines form a separate partition; and

a short vector mode in which the vector register elements of each of said function pipes form a separate partition.