CO-PROCESSOR INFRASTRUCTURE SUPPORTING DYNAMICALLY-MODIFIABLE PERSONALITIES

• US 20100115237A1
• Filed: 10/31/2008
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Lenovo PC International Limited (Lenovo Group Ltd.), Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Wallach, Steven J., Brewer, Tony
• Granted Patent: US 8,205,066 B2
• Time in Patent Office: Days
• US Class Current: 712/34
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.

Claims

1. A method for processing data comprising:

configuring an existing virtual memory and instruction decode infrastructure that is common to a plurality of personalities with application-specific function units.

2. The method of claim 1 wherein said existing virtual memory and instruction decode infrastructure is a virtual memory and instruction decode infrastructure of a co-processor.

3. The method of claim 2 further comprising:

receiving, by the co-processor, reconfiguration information pertaining to the application-specific personality.

4. The method of claim 3 wherein the receiving is performed dynamically during execution of an application for which the application-specific personality is desired.

5. The method of claim 1 wherein the function units are compatible with the framework of the infrastructure, said infrastructure including virtual memory, physical memory, instruction structure and a register structure.

6. The method of claim 1 wherein said plurality of personalities comprise a plurality of vector processing personalities.

7. The method of claim 6 wherein said plurality of vector processing personalities comprise at least one of a single-precision vector processing personality and a double-precision vector processing personality.

8. The method of claim 1 wherein said configuring comprising:

configuring at least one application engine of a co-processor with application-specific function units for performing operations desired for a selected one of a plurality of different vector processing personalities, wherein said existing virtual memory and instruction decode infrastructure of the co-processor is common across all of the plurality of different vector processing personalities.

9. A system for processing data comprising:

at least one application engine having at least one configurable function unit that is configurable to any of a plurality of different application-specific personalities; and

a virtual memory and instruction decode infrastructure common to all the plurality of different application-specific personalities.

10. The system of claim 9 comprising:

a co-processor comprising said at least one application engine and said virtual memory and instruction decode infrastructure.

11. The system of claim 10 further comprising:

at least one host processor.

12. The system of claim 11 wherein at least a portion of instructions of an executable being executed by said at least one host processor are dispatched for processing by said co-processor.

13. The system of claim 9 wherein the plurality of different application-specific personalities comprise a plurality of different vector processing personalities.

14. The system of claim 13 wherein said plurality of different vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

15. A co-processor comprising:

at least one application engine having at least one configurable function unit that is configurable to any of a plurality of different application-specific vector processing personalities; and

a co-processor infrastructure common to all the plurality of different application-specific vector processing personalities.

16. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a memory management infrastructure, where said memory management infrastructure is common to all the plurality of different application-specific vector processing personalities.

17. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a system interface infrastructure for interfacing with a host processor, where said system interface infrastructure is common to all the plurality of different application-specific vector processing personalities.

18. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

an instruction decode infrastructure, where said instruction decode infrastructure is common to all the plurality of different application-specific vector processing personalities.

19. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different application-specific vector processing personalities.

20. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a memory management infrastructure, a system interface infrastructure for interfacing with a host processor, and an instruction decode infrastructure that are common to all the plurality of different application-specific vector processing personalities.

21. The co-processor of claim 20 wherein the co-processor infrastructure further comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different application-specific vector processing personalities.

22. The co-processor of claim 15 wherein said plurality of different application-specific vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

23. A multi-processor system comprising:

a host processor; and

a co-processor, said co-processor including

at least one configurable function unit that is configurable to any of a plurality of different vector processing personalities, and

a virtual memory and instruction decode infrastructure that is common to all the plurality of different vector processing personalities.

24. The multi-processor system of claim 23 wherein said plurality of different vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

25. A multi-processor system comprising:

a plurality of processors comprising at least a host processor and a dynamically reconfigurable co-processor, wherein the host processor and dynamically reconfigurable co-processor each process a portion of instructions of an executable file; and

said dynamically reconfigurable co-processor comprising reconfigurable function units that can be dynamically configured for performing corresponding operations of any of a plurality of different vector processing personalities; and

said dynamically reconfigurable co-processor further comprising an infrastructure that is common to all the plurality of different vector processing personalities.

26. The multi-processor system of claim 25 wherein the infrastructure comprises:

a memory management infrastructure, a system interface infrastructure for interfacing with said host processor, and an instruction decode infrastructure that are common to all the plurality of different vector processing personalities.

27. The multi-processor system of claim 26 wherein the infrastructure further comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different vector processing personalities.

28. The co-processor of claim 25 wherein said plurality of different vector processing personalities comprise at least:

a single-precision vector processing personality and a double-precision vector processing personality.

29. A method comprising:

initiating an executable file for processing instructions of the executable file by a multi-processor system, wherein the multi-processor system comprises at least one host processor and at least one reconfigurable co-processor;

configuring said at least one reconfigurable co-processor with a selected one of a plurality of different vector processing personalities for processing a portion of the instructions of the executable file, wherein the selected vector processing personality differs from an instruction set of the at least one host processor;

processing, by the multi-processor system, the instructions of the executable file, wherein a portion of the instructions are processed by the at least one host processor and a portion of the instructions are processed by the at least one reconfigurable co-processor.

30. The method of claim 29 wherein said plurality of different vector processing personalities comprise at least:

a single-precision vector processing personality and a double-precision vector processing personality.

31. A method comprising:

initiating an executable file for processing instructions of the executable file by a multi-processor system, wherein the multi-processor system comprises at least one host processor and at least one dynamically reconfigurable co-processor;

determining one of a plurality of different vector processing personalities to load to said at least one dynamically reconfigurable co-processor for processing a portion of the instructions of the executable file, wherein the determined vector processing personality defines an instruction set that comprises instructions for performing vector oriented operations;

when determined that the determined vector processing personality is not present on the dynamically reconfigurable co-processor, loading the determined vector processing personality to the dynamically reconfigurable co-processor; and

processing, by the multi-processor system, the instructions of the executable file, wherein a portion of the instructions are processed by the at least one host processor and a portion of the instructions are processed by the at least one dynamically reconfigurable co-processor.

32. The method of claim 31 wherein said plurality of different vector processing personalities comprise at least:

a single-precision vector processing personality and a double-precision vector processing personality.

33. A multi-processor system comprising:

a host processor comprising a first instruction set; and

a co-processor comprising reconfigurable logic for dynamically reconfiguring the co-processor to possess any of a plurality of different vector processing personalities.

34. The multi-processor system of claim 33 wherein said host processor and said co-processor share a common virtual address space.

35. The multi-processor system of claim 34 further comprising:

each of said host processor and said co-processor comprising a respective local cache, wherein cache coherency is maintained between the host processor and co-processor.

36. The multi-processor system of claim 33 further comprising:

an executable file comprising instructions, wherein a portion of said instructions are for processing by said host processor and a portion of said instructions are for processing by said co-processor.

37. The multi-processor system of claim 36 wherein all memory addresses for all of said instructions in the executable are virtual addresses.