CPU POWER DELIVERY SYSTEM

• US 20100115301A1
• Filed: 01/08/2010
• Published: 05/06/2010
• Est. Priority Date: 09/30/2004
• Status: Abandoned Application

• Current Assignee: Donald S. Gardner, Gerhard Schrom, Howard A. Wilson, Nitin Borkar, Peter Hazucha, Shekhar Y. Borkar, Siva G. Narendra, Tanay Karnik, Vivek K. De
• Original Assignee: Donald S. Gardner, Gerhard Schrom, Howard A. Wilson, Nitin Borkar, Peter Hazucha, Shekhar Y. Borkar, Siva G. Narendra, Tanay Karnik, Vivek K. De
• Inventors: Borkar, Nitin, Narendra, Siva G., Gardner, Donald S., Schrom, Gerhard, Hazucha, Peter, Karnik, Tanay, Wilson, Howard A., Borkar, Shekhar Y., De, Vivek K.
• Application Number:
  US12/684,257
• Publication Number:
  US 20100115301A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/189 Power distribution
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.

Claims

1. A central processing unit (CPU) comprising:

a CPU die, including;

a first processing core;

a second processing core; and

a voltage regulator die bonded to the CPU die in a three dimensional packaging configuration, including;

a first voltage regulator module (VRM) to supply a first voltage to the first processing core; and

a second VRM to supply a second voltage to the second processing core.

2. The CPU of claim 1 wherein the first voltage is equal to the second voltage.

3. The CPU of claim 1 wherein the voltage regulator die further comprises:

a third VRM to supply a third voltage to a cache at the CPU die; and

a fourth VRM to supply a fourth voltage to an input/output (I/O) circuitry at the CPU die.

4. The CPU of claim 3 further comprising I/O connections coupled between the voltage regulator die and the CPU die.

5. The CPU of claim 1 further comprising a package substrate bonded to the voltage regulator die.

6. The CPU of claim 5 wherein the voltage regulator die is pad matched to the CPU die and the package substrate.

7. The CPU of claim 1 wherein the voltage regulator die is flipped and bonded to the CPU die metal side to metal side.

8. A method comprising bonding a voltage regulator die to a central processing unit (CPU) die in a three-dimensional packaging configuration.

9. The method of claim 8 further comprising bonding a package substrate to the voltage regulator die.

10. The method of claim 9 wherein the voltage regulator die is pad matched to the CPU die and the package substrate.

11. The method of claim 8 further comprising coupling I/O connections between the voltage regulator die and the CPU die.

12. The method of claim 8 further comprising:

supplying a first voltage to a first processing core on the CPU die with a first voltage regulator module (VRM) on the voltage regulator die; and

supplying a second voltage to a second processing core on the CPU die with a second VRM on the voltage regulator die

13. A system comprising:

a central processing unit (CPU) having;

a CPU die, including;

a first processing core;

a second processing core; and

a voltage regulator die bonded to the CPU die in a three dimensional packaging configuration, including;

a first voltage regulator module (VRM) to supply a first voltage to the first processing core;

a second VRM to supply a second voltage to the second processing core;

a chipset coupled to the CPU; and

a main memory device coupled to the chipset.

14. The system of claim 13 wherein the voltage regulator die further comprises:

a third VRM to supply a third voltage to a cache at the CPU die; and

a fourth VRM to supply a fourth voltage to an input/output (I/O) circuitry at the CPU die.

15. The system of claim 14 further comprising I/O connections coupled between the voltage regulator die and the CPU die.

16. The system of claim 13 wherein the CPU further comprises a package substrate bonded to the voltage regulator die.

18. The system of claim 13 wherein the voltage regulator die is flipped and bonded to the CPU die metal side to metal side.

17. The system of claim 65 wherein the voltage regulator die is pad matched to the CPU die and the package substrate.