POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES

• US 20100115304A1
• Filed: 10/31/2008
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Intel Corporation
• Inventors: Finkelstein, Lev, Rotem, Efraim, Ronen, Ronny, Cohen, Aviad, Rajwan, Doron
• Granted Patent: US 8,402,290 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus relating to power management for multiple processor cores are described. In one embodiment, one or more techniques may be utilized locally (e.g., on a per core basis) to manage power consumption in a processor. In another embodiment, power may be distributed among different power planes of a processor based on energy-based considerations. Other embodiments are also disclosed and claimed.

Claims

1. An apparatus comprising:

a processor having a plurality of processor cores;

a single power plane to supply power to more than one of the plurality of processor cores; and

a power management logic to cause a modification to an operational characteristic of at least one processor core of the plurality of processor cores in response to;

a detection of excessive temperature at the least one processor core; and

a determination of which one of the other processor cores of the plurality of processor cores are active and at a temperature value.

2. The apparatus of claim 1, wherein the temperature value is below an excessive threshold temperature value.

3. The apparatus of claim 1, wherein the power management logic is to cause:

a reduction of voltage supplied to more than one cores of the processor and a reduction of the operational characteristic of the at least one processor core.

4. The apparatus of claim 1, wherein the operation characteristic of the at least one processor core comprises one or more of:

an operating voltage and an operating frequency.

5. The apparatus of claim 1, further comprising one or more sensors to detect variations, corresponding to one or more of the plurality of processor cores, in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

6. The apparatus of claim 1, further comprising a voltage regulator to supply power to more than one cores of the processor via the single power plane.

7. The apparatus of claim 1, wherein the plurality of processor cores consist essentially of 3 or more processor cores.

8. The apparatus of claim 1, wherein the processor and the power management logic are on a single integrated circuit.

9. The apparatus of claim 1, wherein the power management logic is to determine an energy budget for each of a plurality of power planes based on:

an energy remainder of a corresponding power plane of a plurality of power planes that indicates how much energy remained unconsumed during a previous time period; and

one or more of a plurality of constraints corresponding to each of the plurality of power planes.

10. An apparatus comprising:

a processor having a plurality of processor cores;

a plurality of power planes to supply power to the plurality of processor cores; and

a power management logic to determine an energy budget for each of the plurality of power planes based on;

an energy remainder of a corresponding power plane of the plurality of power planes that indicates how much energy remained unconsumed during a previous time period; and

one or more of a plurality of constraints corresponding to each of the plurality of power planes.

11. The apparatus of claim 10, wherein the power management logic is to determine the energy reminder based on a thermal design power (TDP) limit during the time period.

12. The apparatus of claim 10, wherein the power management logic is to determine the energy reminder based on an amount of power spent over the time period.

13. The apparatus of claim 10, wherein the power management logic is to determine the energy reminder based on a decay component.

14. The apparatus of claim 10, wherein the power management logic is to determine an energy budget for each of the plurality of power planes based on all of the plurality of constraints.

15. The apparatus of claim 10, further comprising one or more sensors to detect variations, corresponding to one or more of the plurality of processor cores, in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

16. The apparatus of claim 10, further comprising a voltage regulator to supply power to the processor via the plurality of power planes.

17. The apparatus of claim 10, wherein the power management logic to cause a modification to an operational characteristic of at least one processor core of the plurality of processor cores in response to:

a detection of excessive temperature at the least one processor core; and

a determination of which one of the other processor cores of the plurality of processor cores are active and at a temperature value.

18. The apparatus of claim 17, wherein the temperature value is below an excessive threshold temperature value.

19. The apparatus of claim 17, wherein the power management logic is to cause:

a reduction of voltage supplied to more than one cores of the processor and a reduction of the operational characteristic of the at least one processor core.

20. A method comprising:

determining whether to modify an operational characteristic of at least one processor core of a plurality of processor cores in response to;

a detection of excessive temperature at the least one processor core and a determination of which one of the other processor cores of the plurality of processor cores are active and at a temperature value; and

determining an energy budget for one or more power planes, coupled to supply power to the plurality of processor cores, based on;

an energy remainder of a corresponding power plane of the one or more power planes that indicates how much energy remained unconsumed during a previous time period and one or more constraints corresponding to each of the one or more power planes.

21. The method of claim 20, wherein the temperature value is below an excessive threshold temperature value.

22. The method of claim 20, wherein the operation characteristic of the at least one processor core comprises one or more of:

an operating voltage and an operating frequency.

23. The method of claim 20, further comprising detecting variations, corresponding to one or more of the plurality of processor cores, in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

24. The method of claim 20, wherein determining the energy budget for one or more power planes is performed based on one or more of:

a thermal design power (TDP) limit during the time period;

an amount of power spent over the time period; and

a decay component.

25. A system comprising:

a processor having a plurality of processor cores;

one or more power planes to supply power to the plurality of processor cores;

a voltage regulator to supply power to the plurality of processor cores via the one or more power planes; and

a power management logic to;

determine whether to modify an operational characteristic of at least one processor core of a plurality of processor cores in response to;

a detection of excessive temperature at the least one processor core and a determination of which one of the other processor cores of the plurality of processor cores are active and at a temperature value; and

determine an energy budget for one or more power planes, coupled to supply power to the plurality of processor cores, based on;

an energy remainder of a corresponding power plane of the one or more power planes that indicates how much energy remained unconsumed during a previous time period and one or more constraints corresponding to each of the one or more power planes.

26. The system of claim 25, further comprising one or more sensors to detect variations, corresponding to one or more of the plurality of processor cores, in one or more of:

temperature, operating frequency, operating voltage, and power consumption.

27. The system of claim 25, wherein the temperature value is below an excessive threshold temperature value.

28. The system of claim 25, wherein the power management logic is to cause:

a reduction of voltage supplied to more than one cores of the processor and a reduction of the operational characteristic of the at least one processor core.

29. The system of claim 25, wherein the power management logic is to determine the energy remainder based on one or more of:

a thermal design power (TDP) limit during the time period;

an amount of power spent over the time period; and

a decay component.

30. The system of claim 25, further comprising an audio device.