Disk Array Control Apparatus and Information Processing Apparatus

• US 20100115321A1
• Filed: 10/19/2009
• Published: 05/06/2010
• Est. Priority Date: 10/31/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Shingo, Muramatsu, Tatsuya, Sonan, Tsutomu
• Application Number:
  US12/581,776
• Publication Number:
  US 20100115321A1
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, a disk array control apparatus includes a volatile memory configured to temporarily store data sent or received by a disk array controller, a first power supply generation circuit configured to generate second power to drive the volatile memory from first power, a second power supply generation circuit configured to generate fourth power to drive the volatile memory from power having a higher voltage selected from the first power and third power supplied from a battery, a first switch configured to interpose in a path flowing the second power, a second switch configured to interpose in a path through which flowing the fourth power, and a power supply switching control unit includes a logic circuit which controls on/off switching of the first switch and the second switch based on a state of a initialization signal.

Claims

1. A disk array control apparatus comprising:

an expansion board inserted into an expansion slot provided in a main board provided in an information processing apparatus comprising a power supply device and a power supply monitoring circuit outputting an initialization signal when the output voltage of the power supply device becomes lower than a set value;

a disk array controller mounted on the expansion board;

a volatile memory configured to temporarily store data sent or received by the disk array controller;

a first power supply generation circuit configured to generate second power having a voltage required to drive the volatile memory from first power supplied from the main board;

a second power supply generation circuit configured to generate fourth power having a voltage required to drive the volatile memory from power having a higher voltage selected from the first power and third power supplied from a battery mounted on the expansion board;

a first switch configured to interpose in a path through which the first power supply generation circuit is connected to the volatile memory;

a second switch configured to interpose in a path through which the second power supply generation circuit is connected to the volatile memory; and

a power supply switching control unit having a logic circuit which controls on/off switching of the first switch and the second switch based on a state of the initialization signal.

2. The apparatus of claim 1, wherein the power supply switching control unit comprises a power supply switching control module configured to turn off the first switch and to turn on the second switch when the initialization signal is low, to turn on the first switch and to turn off the second switch when the initialization signal changes from low to high, and to turn off the first switch and to turn on the second switch when the initialization signal changes from high to low.

3. The apparatus of claim 2, wherein the power supply switching control module is configured to turn on the first switch after turning off the second switch when the initialization signal is changed from high to low.

4. The apparatus of claim 3, wherein the power supply switching control module comprising:

a delay circuit configured to be input the initialization signal and to output a delayed initialization signal obtained by delaying the input initialization signal;

a NAND gate configured to receive the initialization signal and the delayed initialization signal, the output signal thereof becoming a control signal for the first switch; and

an OR gate configured to receive the initialization signal and the delayed initialization signal, the output signal thereof becoming a control signal for the second switch.

5. An information processing apparatus comprising:

a power supply device configured to output first power;

a main board;

a first power supply circuit provided on the main board and configured to generate second power from first power supplied from the power supply device;

a power supply monitoring circuit configured to output an initialization signal when the voltage of the first power is less than a set value;

an expansion slot provided in the main board; and

a power supply switching control unit comprising an expansion board inserted into the expansion slot, a disk array controller mounted on the expansion board, a volatile memory configured to temporarily stores data sent or received by the disk array controller, a first power supply generation circuit configured to generate second power having a voltage required to drive the volatile memory from the first power supplied from the main board, a second power supply generation circuit configured to generate fourth power having a voltage required to drive the volatile memory from power having a higher voltage selected from the first power and third power supplied from a battery mounted on the expansion board, a first switch configured to interpose in a path through which the first power supply generation circuit is connected to the volatile memory, a second switch configured to interposed in a path through which the second power supply generation circuit is connected to the volatile memory, and a logic circuit configured to receive the initialization signal and controls on/off switching of the first switch and the second switch in accordance with the initialization signal.

6. The apparatus of claim 5, wherein the power supply switching control unit comprises a power supply switching control module configured to turn off the first switch and to turn on the second switch when the initialization signal is low, to turn on the first switch and turns off the second switch when the initialization signal is changed from low to high, and to turn off the first switch and to turn on the second switch when the initialization signal is changed from high to low.

7. The apparatus of claim 6, wherein the power supply switching control module is configured to turn on the first switch after turning off the second switch when the initialization signal is changed from high to low.

8. The apparatus of claim 7, wherein the power supply switching control module comprising:

a delay circuit configured to be input the initialization signal and to output a delayed initialization signal obtained by delaying the input initialization signal;

a NAND gate configured to receive the initialization signal and the delayed initialization signal, the output signal thereof becoming a control signal for the first switch; and

an OR gate configured to receive the initialization signal and the delayed initialization signal, the output signal thereof becoming a control signal for the second switch.