METHOD FOR ACCESSING A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF

• US 20100115325A1
• Filed: 01/21/2009
• Published: 05/06/2010
• Est. Priority Date: 10/30/2008
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Lin, Jen-Wen
• Granted Patent: US 7,979,737 B2
• Time in Patent Office: Days
• US Class Current: 714/2
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A method for accessing a Flash memory including a plurality of blocks includes: selectively programming a page in a first block of the blocks; when a status of the Flash memory is abnormal, determining whether a number of error bits is less than a predetermined value; and when the number of error bits is not less than the predetermined value, moving the first block. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. In addition, when the number of error bits is not less than the predetermined value, the controller that executes the program code by utilizing the microprocessor moves the first block.

Claims

1. A method for accessing a Flash memory comprising a plurality of blocks, the method comprising:

selectively programming a page in a first block of the blocks;

when a status of the Flash memory is abnormal, determining whether a number of error bits is less than a predetermined value; and

when the number of error bits is not less than the predetermined value, moving the first block.

2. The method of claim 1, wherein the step of determining whether the number of error bits is less than the predetermined value further comprises:

when the status of the Flash memory is abnormal, reading an error bit count from an error correction code (ECC) register to determine whether the number of error bits is less than the predetermined value, wherein the error bit count represents the number of error bits.

3. The method of claim 1, further comprising:

reading a status register of the Flash memory to determine whether the status of the Flash memory is abnormal.

4. The method of claim 1, wherein the predetermined value corresponds to specifications of the Flash memory.

5. The method of claim 1, further comprising:

as long as the first block is moved, determining whether at least one error bit is an error correctable by error correction codes (ECCs); and

when the at least one error bit is not an error correctable by ECCs, marking the first block as a bad block.

6. The method of claim 1, further comprising:

reading a page in a second block of the blocks; and

determining whether at least one error bit that occurs during reading is an error correctable by error correction codes (ECCs);

wherein the step of selectively programming the page in the first block of the blocks further comprises;

when the at least one error bit that occurs during reading is an error correctable by ECCs, programming the same page of the reading step in the first block of the blocks.

7. The method of claim 6, further comprising:

when the at least one error bit that occurs during reading is not an error correctable by ECCs, selectively re-reading the page.

8. A memory device, comprising:

a Flash Memory comprising a plurality of blocks; and

a controller for accessing the Flash Memory, wherein the controller selectively programs a page in a first block of the blocks;

wherein when a status of the Flash memory is abnormal, the controller determines whether a number of error bits is less than a predetermined value; and

when the number of error bits is not less than the predetermined value, the controller moves the first block.

9. The memory device of claim 8, wherein when the status of the Flash memory is abnormal, the controller reads an error bit count from an error correction code (ECC) register within the controller to determine whether the number of error bits is less than the predetermined value;

and the error bit count represents the number of error bits.

10. The memory device of claim 8, wherein the controller reads a status register of the Flash memory to determine whether the status of the Flash memory is abnormal.

11. The memory device of claim 8, wherein the predetermined value corresponds to specifications of the Flash memory.

12. The memory device of claim 8, wherein as long as the controller moves the first block, the controller determines whether at least one error bit is an error correctable by error correction codes (ECCs);

and when the at least one error bit is not an error correctable by ECCs, the controller marks the first block as a bad block.

13. The memory device of claim 8, wherein the controller reads a page in a second block of the blocks, and determines whether at least one error bit that occurs during reading is an error correctable by error correction codes (ECCs);

and when the at least one error bit that occurs during reading is an error correctable by ECCs, the controller programs the same page of the reading operation in the first block of the blocks.

14. The memory device of claim 13, wherein when the at least one error bit that occurs during reading is not an error correctable by ECCs, the controller selectively re-reads the page.

15. A controller of a memory device, the controller being utilized for accessing a Flash Memory comprising a plurality of blocks, the controller comprising:

a read only memory (ROM) arranged to store a program code; and

a microprocessor arranged to execute the program code to control the access to the Flash memory;

wherein the controller that executes the program code by utilizing the microprocessor selectively programs a page in a first block of the blocks;

when a status of the Flash memory is abnormal, the controller that executes the program code by utilizing the microprocessor determines whether a number of error bits is less than a predetermined value; and

when the number of error bits is not less than the predetermined value, the controller that executes the program code by utilizing the microprocessor moves the first block.

16. The controller of claim 15, wherein when the status of the Flash memory is abnormal, the controller that executes the program code by utilizing the microprocessor reads an error bit count from an error correction code (ECC) register within the controller to determine whether the number of error bits is less than the predetermined value;

and the error bit count represents the number of error bits.

17. The controller of claim 15, wherein the controller that executes the program code by utilizing the microprocessor reads a status register of the Flash memory to determine whether the status of the Flash memory is abnormal.

18. The controller of claim 15, wherein the predetermined value corresponds to specifications of the Flash memory.

19. The controller of claim 15, wherein as long as the controller that executes the program code by utilizing the microprocessor moves the first block, the controller determines whether at least one error bit is an error correctable by error correction codes (ECCs);

and when the at least one error bit is not an error correctable by ECCs, the controller that executes the program code by utilizing the microprocessor marks the first block as a bad block.

20. The controller of claim 15, wherein the controller that executes the program code by utilizing the microprocessor reads a page in a second block of the blocks, and determines whether at least one error bit that occurs during reading is an error correctable by error correction codes (ECCs);

and when the at least one error bit that occurs during reading is an error correctable by ECCs, the controller that executes the program code by utilizing the microprocessor programs the same page of the reading operation in the first block of the blocks.

21. The controller of claim 20, wherein when the at least one error bit that occurs during reading is not an error correctable by ECCs, the controller that executes the program code by utilizing the microprocessor selectively re-reads the page.