AUTOMATIC DEFECT MANAGEMENT IN MEMORY DEVICES
First Claim
1. A method for storing data in a memory that includes analog memory cells, comprising:
- identifying one or more defective memory cells in a group of the analog memory cells;
selecting an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells; and
encoding the data using the selected ECC and storing the encoded data in the group of the analog memory cells.
2 Assignments
0 Petitions
Accused Products
Abstract
A method for storing data in a memory (28) that includes analog memory cells (32) includes identifying one or more defective memory cells in a group of the analog memory cells. An Error Correction Code (ECC) is selected responsively to a characteristic of the identified defective memory cells. The data is encoded using the selected ECC and the encoded data is stored in the group of the analog memory cells. In an alternative method, an identification of one or more defective memory cells among the analog memory cells is generated. Analog values are read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells. The analog values are processed using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.
325 Citations
54 Claims
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1. A method for storing data in a memory that includes analog memory cells, comprising:
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identifying one or more defective memory cells in a group of the analog memory cells; selecting an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells; and encoding the data using the selected ECC and storing the encoded data in the group of the analog memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method for operating a memory, comprising:
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encoding data using an Error Correction Code (ECC); storing the encoded data as first analog values in respective analog memory cells of the memory; generating an identification of one or more defective memory cells among the analog memory cells; after storing the encoded data, reading from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells, respective second analog values; and processing the second analog values using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data. - View Dependent Claims (23, 24, 25)
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26. A data storage apparatus, comprising:
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an interface, which is coupled to communicate with a memory that includes a plurality of analog memory cells; and a processor, which is coupled to identify one or more defective memory cells in a group of the analog memory cells, to select an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells, to encode the data using the selected ECC and to store the encoded data in the group of the analog memory cells. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A data storage apparatus, comprising:
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an interface, which is coupled to communicate with a memory; and a processor, which is coupled to encode data using an Error Correction Code (ECC), to store the encoded data as first analog values in respective analog memory cells of the memory, to generate an identification of one or more defective memory cells among the analog memory cells, to read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells, respective second analog values, and to process the second analog values using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data. - View Dependent Claims (48, 49, 50)
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51. A data storage apparatus, comprising:
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a memory, which comprises a plurality of analog memory cells; and a processor, which is connected to the memory and is coupled to identify one or more defective memory cells in a group of the analog memory cells, to select an Error Correction Code (ECC) responsively to a characteristic of the identified defective memory cells, to encode the data using the selected ECC and to store the encoded data in the group of the analog memory cells. - View Dependent Claims (52, 53)
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54. A data storage apparatus, comprising:
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a memory, which comprises a plurality of analog memory cells; and a processor, which is connected to the memory and is coupled to encode data using an Error Correction Code (ECC), to store the encoded data as first analog values in respective analog memory cells of the memory, to generate an identification of one or more defective memory cells among the analog memory cells, to read from the analog memory cells in which the encoded data were stored, including at least one of the defective memory cells, respective second analog values, and to process the second analog values using an ECC decoding process responsively to the identification of the at least one of the defective memory cells, so as to reconstruct the data.
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Specification