BACK-ILLUMINATED CMOS IMAGE SENSORS

• US 20100116971A1
• Filed: 11/07/2008
• Published: 05/13/2010
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: McCarten, John P., Stevens, Eric G., Anderson, Todd J., Summa, Joseph R., Tivarus, Cristian A.
• Granted Patent: US 8,618,458 B2
• Time in Patent Office: Days
• US Class Current: 250/214.100
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A back-illuminated image sensor includes a sensor layer disposed between an insulating layer and a circuit layer electrically connected to the sensor layer. An imaging area includes a plurality of photodetectors is formed in the sensor layer and a well that spans the imaging area. The well can be disposed between the backside of the sensor layer and the photodetectors, or the well can be a buried well formed adjacent to the backside of the sensor layer with a region including formed between the photodetectors and the buried well. One or more side wells can be formed laterally adjacent to each photodetector. The dopant in the well has a segregation coefficient that causes the dopant to accumulate on the sensor layer side of an interface between the sensor layer and the insulating layer.

Claims

1. A back-illuminated image sensor, comprising:

a sensor layer disposed between an insulating layer and a circuit layer electrically connected to the sensor layer, wherein a frontside of the sensor layer is adjacent to the circuit layer and a backside of the sensor layer is adjacent to the insulating layer;

an imaging area including a plurality of photodetectors for converting light incident on the backside of the sensor layer into photo-generated charges, wherein the plurality of photodetectors are doped with a p-type dopant and are disposed in the sensor layer adjacent to the frontside of the sensor layer; and

a well spanning the imaging area and formed in at least a portion of the sensor layer adjacent to the backside of the sensor layer, wherein the well is doped with an n-type dopant having a segregation coefficient that causes the n-type dopant to accumulate on the sensor layer side of an interface between the backside of the sensor layer and the insulating layer.

2. The back-illuminated image sensor of claim 1, further comprising a support substrate bonded to the circuit layer.

3. The back-illuminated image sensor of claim 1, wherein the well comprises a buried well.

4. The back-illuminated image sensor of claim 3, further comprising a first side well formed laterally adjacent to and on one side of each photodetector, and a second side well formed laterally adjacent to and on the opposing side of each photodetector, wherein the first and second side wells are doped with an n-type dopant.

5. The back-illuminated image sensor of claim 4, further comprising a region doped with a p-type dopant disposed between the buried well, each photodetector, and respective first and second side wells.

6. The back-illuminated image sensor of claim 5, wherein the n-type dopant comprises one of a phosphorus dopant, an antimony dopant, and an arsenic dopant.

7. The back-illuminated image sensor of claim 1, wherein the sensor layer comprises a silicon layer.

8. The back-illuminated image sensor of claim 1, wherein the n-type dopant in the well has a dopant gradient configured to drive the photo-generated charges into respective photodetectors nearest the photo-generated charges.

9. The back-illuminated image sensor of claim 1, wherein the well is biased at a predetermined potential.

10. An image capture device, comprising:

a back-illuminated image sensor, including;

a sensor layer disposed between an insulating layer and a circuit layer electrically connected to the sensor layer, wherein a frontside of the sensor layer is adjacent to the circuit layer and a backside of the sensor layer is adjacent to the insulating layer;

an imaging area including a plurality of photodetectors for converting light incident on the backside of the sensor layer into photo-generated charges, wherein the plurality of photodetectors are doped with a p-type dopant and are disposed adjacent to the frontside of the sensor layer; and

a well spanning the imaging area and formed in at least a portion of the sensor layer adjacent to the backside of the sensor layer, wherein the well is doped with an n-type dopant having a segregation coefficient that causes the n-type dopant to accumulate on the sensor layer side of an interface between the backside of the sensor layer and the insulating layer.

11. The back-illuminated image sensor of claim 10, wherein the well comprises a buried well.

12. The back-illuminated image sensor of claim 11, further comprising a first side well formed laterally adjacent to and on one side of each photodetector, and a second side well formed laterally adjacent to and on the opposing side of each photodetector, wherein the first and second side wells are doped with an n-type dopant.

13. The back-illuminated image sensor of claim 12, further comprising a region doped with a p-type dopant disposed between the buried well, each photodetector, and respective first and second side wells.

14. The back-illuminated image sensor of claim 13, wherein the n-type dopant in the well has a dopant gradient configured to drive the photo-generated charges into respective photodetectors nearest the photo-generated charges.

15. The back-illuminated image sensor of claim 10, wherein the well is biased at a predetermined potential.

16. A method for fabricating a back-illuminated image sensor that includes a sensor layer disposed between an insulating layer and a circuit layer electrically connected to the sensor layer, wherein a frontside of the sensor layer is adjacent to the circuit layer and a backside of the sensor layer is adjacent to the insulating layer, the method comprising the steps of:

doping the sensor layer with a n-type dopant to form a well in at least a portion of the sensor layer adjacent to the backside of the sensor layer, wherein the n-type dopant has a segregation coefficient that causes the n-type dopant to accumulate on the sensor layer side of an interface between the backside of the sensor layer and the insulating layer; and

doping the sensor layer with a p-type dopant to form a plurality of photodetectors that convert light incident on the backside of the sensor layer into photo-generated charges, wherein the plurality of photodetectors are formed adjacent to the frontside of the sensor layer.

17. The method of claim 16, wherein the step of doping the sensor layer with a n-type dopant to form a well comprises implanting the sensor layer with an n-type dopant to form a well in at least a portion of the sensor layer adjacent to the backside of the sensor layer.

18. The method of claim 17, wherein the step of implanting the sensor layer with an n-type dopant to form a well comprises implanting the sensor layer with an n-type dopant to form a buried well in a portion of the sensor layer adjacent to the backside of the sensor layer.

19. The method of claim 18, further comprising the step of doping the sensor layer with an n-type dopant to form a first side well laterally adjacent to and on one side of each photodetector and a second side well laterally adjacent to and on the opposing side of each photodetector.

20. The method of claim 19, wherein the buried well and first and second side wells are formed such that a region doped with a p-type dopant is disposed between the buried well, each photodetector and the respective first and second side wells.