SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20100117077A1
• Filed: 11/06/2009
• Published: 05/13/2010
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, YAMAZAKI, Shunpei, KAWAE, Daisuke
• Granted Patent: US 8,373,164 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. A semiconductor device comprising:

a gate electrode formed over a substrate having an insulating surface;

an insulating layer formed over the gate electrode;

source and drain electrodes formed over the insulating layer; and

an oxide semiconductor layer formed between a side surface of the source electrode and a side surface of the drain electrode, which face each other, so as to overlap with the gate electrode with the insulating layer interposed therebetween,

wherein the oxide semiconductor layer is in contact with at least the respective side surfaces of the source and drain electrodes, and

wherein a first angle formed between a surface of the substrate and the side surface of the source electrode and a second angle formed between the surface of the substrate and the side surface of the drain electrode are each greater than or equal to 20° and

less than 90°

.

2. The semiconductor device according to claim 1, further comprising a buffer layer over the source and drain electrodes,

wherein the oxide semiconductor layer is provided over the buffer layer.

3. The semiconductor device according to claim 1, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains at least one material selected from the group consisting of indium, gallium, and zinc.

5. A semiconductor device comprising:

a gate electrode formed over a substrate having an insulating surface;

an insulating layer formed over the gate electrode;

source and drain electrodes formed over the insulating layer; and

an oxide semiconductor layer formed between a side surface of the source electrode and a side surface of the drain electrode, which face each other, so as to overlap with the gate electrode with the insulating layer interposed therebetween,

wherein the oxide semiconductor layer is in contact with at least the respective side surfaces of the source and drain electrodes, and

wherein a first angle formed between a surface of the substrate and a side surface of a first bottom edge of the source electrode and a second angle formed between the surface of the substrate and a side surface of a second bottom edge of the drain electrode are each greater than or equal to 20° and

less than 90°

.

6. The semiconductor device according to claim 5, wherein the first angle formed between the surface of the substrate and the side surface of the first bottom edge of the source electrode is made to be different from an angle formed between the surface of the substrate and a side surface of a top edge of the source electrode.

7. The semiconductor device according to claim 5, wherein the second angle formed between the surface of the substrate and the side surface of the second bottom edge of the drain electrode is made to be different from an angle formed between the surface of the substrate and a side surface of a top edge of the drain electrode.

8. The semiconductor device according to claim 5, wherein the side surface of each of the source and drain electrodes has a curved surface at least partly.

9. The semiconductor device according to claim 5, further comprising a buffer layer over the source and drain electrodes,

wherein the oxide semiconductor layer is provided over the buffer layer.

10. The semiconductor device according to claim 5, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

11. The semiconductor device according to claim 5, wherein the oxide semiconductor layer contains at least one material selected from the group consisting of indium, gallium, and zinc.

12. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer to cover the gate electrode;

stacking a conductive layer and a buffer layer over the gate insulating layer without exposure to air;

selectively etching the conductive layer and the buffer layer to form a source and drain electrodes each having a side surface which forms an angle greater than or equal to 20° and

less than 90°

with respect to a surface of the substrate; and

forming an oxide semiconductor layer over the gate insulating layer, the source electrode, and the drain electrode.

13. The method for manufacturing a semiconductor device, according to claim 12, wherein the oxide semiconductor layer contains at least one material selected from the group consisting of indium, gallium, and zinc.

14. The method for manufacturing a semiconductor device, according to claim 12, wherein the buffer layer contains at least one material selected from the group consisting of indium, gallium, and zinc.

15. The method for manufacturing a semiconductor device, according to claim 12, wherein the oxide semiconductor layer and the buffer layer each use a target having the same composition.