SEMICONDUCTOR TEST PAD STRUCTURES

• US 20100117080A1
• Filed: 11/07/2008
• Published: 05/13/2010
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Yu-Wen, Chen, Hsien-Wei, Tsai, Hao-Yi, Jeng, Shin-Puu, Chen, Ying-Ju
• Granted Patent: US 8,013,333 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

Claims

1. An interconnect structure comprising:

a plurality of vertically stacked metal layers, each metal layer including a test pad and an inter-metal dielectric material, the test pads each having a first side and a second opposite side; and

at least a first metallic via bar embedded into the interconnect structure and being configured and arranged to electrically interconnect the test pads in the plurality of metal layers, the via bar engaging each of the test pads near the first side of each test pad and extending horizontally along substantially an entire length of each first side.

2. The interconnect structure of claim 1, wherein the via bar extends vertically through the dielectric material of each metal layer.

3. The interconnect structure of claim 1, wherein the via bar defines a wall-shaped protective barrier that has a vertical height that is at least coextensive with a vertical height of the plurality of metal layers.

4. The interconnect structure of claim 1, further comprising a second via bar embedded into the interconnect structure and being configured and arranged to electrically interconnect the test pads in the plurality of metal layers, the second via bar engaging each of the test pads near the second side of each test pad and extending horizontally along substantially an entire length of each second side.

5. The interconnect structure of claim 4, wherein the first and second via bars are disposed near opposite perimeters of the interconnect structure.

6. The interconnect structure of claim 4, wherein the first and second via bars are disposed on opposite sides of a die singulation saw cut line defined by the test pads.

7. The interconnect structure of claim 1, wherein the via bar has a vertical height, a horizontal length, and horizontal thickness measured perpendicular to the length, the height and length being larger than the thickness.

8. The interconnect structure of claim 1, wherein the plurality of metal layers includes at least three metal layers and the via bar extends vertically through all of the metal layers.

9. The interconnect structure of claim 1, wherein the via bar is made of copper.

10. The interconnect structure of claim 1, wherein a top metal test pad is at least partially covered by a metallic capping layer comprising aluminum or aluminum alloy.

11. The interconnect structure of claim 1, wherein the capping layer is surrounded by a first passivation layer.

12. The interconnect structure of claim 4, further comprising:

a third via bar and a fourth via bar each being arranged at an angle to the first and second via bars, the third and fourth via bars each being embedded into the interconnect structure and engaging each of the test pads, the third via bar extending horizontally along substantially an entire length of a third side of each test pad, the fourth via bar extending horizontally along substantially an entire length of a fourth side of each test pad.

13. The interconnect structure of claim 12, wherein the third and fourth via bars are each connected respectively to the first and second via bars to form a ring-like continuous via bar structure.

14. The interconnect structure of claim 12, wherein the third and fourth via bars are disposed across a die singulation saw cut line defined by the test pads.

15. An interconnect structure package comprising:

a top metal layer including a top test pad having a planar surface and an inter-metal dielectric material disposed below the test pad, the test pad having a first pair of opposing sides each having a first length and a second pair of opposing sides each having a second length;

a second metal layer disposed below the top metal layer, the second metal layer having a second test pad having a planar surface and an inter-metal dielectric material disposed below the second test pad, the second test pad having a first pair of opposing sides each having a first length and a second pair of opposing sides each having a second length; and

a first pair of opposing metallic via bars extending from the top metal test pad to the second metal test to form an electrical interconnection therebetween, at least one of the via bars engaging the top and second test pads along substantially the entire first length of one of the first pair of sides of each of the top and second test pads.

16. The interconnect structure of claim 15, wherein the opposing pair of via bars are arranged in parallel relation to each other.

17. The interconnect structure of claim 15, wherein the remaining via bar engages the top and second test pads along substantially the entire first length of the remaining one of the first pair of sides of each of the top and second test pads.

18. A semiconductor wafer comprising:

a semiconductor substrate;

a plurality of integrated circuit dies formed on the substrate and arranged across a top planar surface of the wafer;

at least one longitudinally-extending scribe band formed between the dies and defining a longitudinally-extending saw cut line for separating the dies from the wafer;

at least one test pad interconnect structure disposed in scribe band and having a portion that extends across the saw cut line, the interconnect structure comprising a plurality of vertically stacked metal layers, each metal layer including a test pad and an inter-metal dielectric material, the test pads each having a first side and a second opposite side; and

at least a first longitudinally-extending metallic via bar embedded into a perimeter portion of the interconnect structure and engaging each of the test pads along substantially the entire first side of each of the test pads.

19. The semiconductor wafer of claim 18, wherein the via bar is arranged parallel to the saw cut line and disposed between the saw cut line and at least one die lying adjacent to the scribe band.

20. The semiconductor wafer of claim 18, further comprising a second longitudinally-extending metallic via bar embedded into the perimeter portion of the interconnect structure and engaging each of the test pads along substantially the entire second side of each of the test pads.