SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

• US 20100117086A1
• Filed: 11/04/2009
• Published: 05/13/2010
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: AKIMOTO, Kengo, TSUBUKU, Masashi
• Granted Patent: US 8,021,917 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a source electrode layer and a drain electrode layer over the gate insulating layer;

performing a plasma treatment on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate in a chamber into which an inert gas is introduced; and

forming an oxide semiconductor layer over the gate insulating layer, the source electrode layer, and the drain electrode layer after the plasma treatment is performed,

wherein the plasma treatment is performed in such a manner that the substrate is provided on one electrode of a pair of electrodes provided in the chamber and a bias voltage is applied to the substrate.

2. The method for manufacturing a semiconductor device, according to claim 1, wherein a high frequency voltage is applied to the one electrode.

3. The method for manufacturing a semiconductor device, according to claim 1, wherein the oxide semiconductor layer is formed by a sputtering method in which a target including indium, gallium, and zinc is used and in which a DC voltage is applied between the substrate and the target.

4. The method for manufacturing a semiconductor device, according to claim 1 and claim 3, wherein the target is provided over the other electrode of the pair of electrodes provided in the chamber, and the plasma treatment and the formation of the oxide semiconductor layer are performed in the chamber in succession.

5. The method for manufacturing a semiconductor device, according to claim 1, wherein by the plasma treatment, a surface layer portion of the gate insulating layer provided between the source electrode layer and the drain electrode layer is removed by 2 nm or more.

6. The method for manufacturing a semiconductor device, according to claim 1, wherein by the plasma treatment, a tapered shape is formed at end portions of the source electrode layer and the drain electrode layer.

7. The method for manufacturing a semiconductor device, according to claim 6, wherein the end portions of the source electrode layer and the drain electrode layer each have a taper angle of greater than or equal to 20°

and less than 90°

.

8. The method for manufacturing a semiconductor device, according to claim 1, wherein by the plasma treatment, a radius of curvature of each upper end portion of the source electrode layer and the drain electrode layer becomes greater than or equal to 1/100 and less than or equal to ½

of a thickness of the source electrode layer or the drain electrode layer.

9. The method for manufacturing a semiconductor device, according to claim 1, wherein an argon gas is used as the inert gas.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a conductive layer over the gate insulating layer;

forming a first oxide semiconductor layer over the conductive layer;

forming a first stack in which the conductive layer and the first oxide semiconductor layer are stacked and a second stack in which the conductive layer and the first oxide semiconductor layer are stacked by etching the conductive layer and the first oxide semiconductor layer;

performing a plasma treatment on surfaces of the gate insulating layer, the first stack, and the second stack which are formed over the substrate in a chamber into which an inert gas is introduced; and

forming a second oxide semiconductor layer over the gate insulating layer, the first stack, and the second stack after the plasma treatment is performed,

wherein the plasma treatment is performed in such a manner that the substrate is provided on one electrode of a pair of electrodes provided in the chamber and a bias voltage is applied to the substrate.

12. The method for manufacturing a semiconductor device, according to claims 10 and 11, wherein a high frequency voltage is applied to the one electrode.

14. The method for manufacturing a semiconductor device, according to claims 10 and 11, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed by a sputtering method in which a target including indium, gallium, and zinc is used and in which a DC voltage is applied between the substrate and the target.

16. The method for manufacturing a semiconductor device, according to claims 10 and 11, wherein conductivity of the first oxide semiconductor layer is higher than conductivity of the second oxide semiconductor layer.

17. The method for manufacturing a semiconductor device, according to claims 10 and 11, wherein an argon gas is used as the inert gas.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming a gate insulating layer over the gate electrode layer;

forming a conductive layer over the gate insulating layer;

performing a first plasma treatment on a surface of the conductive layer;

forming a first oxide semiconductor layer over the conductive layer after the first plasma treatment is performed;

forming a first stack in which the conductive layer and the first oxide semiconductor layer are stacked and a second stack in which the conductive layer and the first oxide semiconductor layer are stacked by etching the conductive layer and the first oxide semiconductor layer;

performing a second plasma treatment on surfaces of the gate insulating layer, the first stack, and the second stack; and

forming a second oxide semiconductor layer over the gate insulating layer, the first stack, and the second stack after the second plasma treatment is performed,

wherein the first plasma treatment and the second plasma treatment are performed in such a manner that the substrate is provided on one electrode of a pair of electrodes provided in a chamber and an inert gas is introduced into the chamber so that a bias voltage is applied to the substrate.

13. The method for manufacturing a semiconductor device, according to claim 11, wherein the formation of the conductive layer, the first plasma treatment, and the formation of the first oxide semiconductor layer are performed in the same chamber in succession.

15. The method for manufacturing a semiconductor device, according to claim 11, wherein the second plasma treatment and the formation of the second oxide semiconductor layer are performed in the same chamber in succession.

18. A semiconductor device comprising:

a gate electrode layer provided over a substrate;

a gate insulating layer provided over the gate electrode layer;

a source electrode layer and a drain electrode layer which are provided over the gate insulating layer; and

an oxide semiconductor layer provided over the gate insulating layer located between the source electrode layer and the drain electrode layer and provided over the source electrode layer and the drain electrode layer,

wherein a thickness of the gate insulating layer located between the source electrode layer and the drain electrode layer is smaller than a thickness of the gate insulating layer located below the source electrode layer and the drain electrode layer, and

wherein end portions of the source electrode layer and the drain electrode layer have tapered shapes, and upper end portions of the source electrode layer and the drain electrode layer have curved surface shapes.

19. The semiconductor device according to claim 18, wherein a thickness of the gate insulating layer located between the source electrode layer and the drain electrode layer is smaller than a thickness of the gate insulating layer located below the source electrode layer and the drain electrode layer by 2 nm or more.

20. The semiconductor device according to claim 18, wherein a taper angle of each end portion of the source electrode layer and the drain electrode layer is greater than or equal to 20°

and less than 90°

.

21. The semiconductor device according to claim 18, wherein a radius of curvature of each upper end portion of the source electrode layer and the drain electrode layer is greater than or equal to 1/100 and less than or equal to ½

of a thickness of the source electrode layer or the drain electrode layer.