ARRAY SUBSTRATE INCLUDING THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME
First Claim
1. A method of fabricating an array substrate, comprising:
- forming a gate line and a gate electrode connected to the gate line;
forming a gate insulating layer on the gate line and the gate insulting layer;
sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode;
forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other;
removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer;
irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion;
forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and
forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
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Accused Products
Abstract
A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
23 Citations
12 Claims
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1. A method of fabricating an array substrate, comprising:
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forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An array substrate for a display device, comprising:
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a substrate; a gate line and a data line on the substrate, the gate line crossing the data line to define a pixel region; a thin film transistor connected to the gate line and the data line, the thin film transistor including an active layer having a first region and a second region at both sides of the first region, the first region including intrinsic polycrystalline silicon, and the second region including intrinsic amorphous silicon; and a pixel electrode in the pixel region and connected to the thin film transistor. - View Dependent Claims (11, 12)
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Specification