SEMICONDUCTOR DEVICES

• US 20100117152A1
• Filed: 01/14/2010
• Published: 05/13/2010
• Est. Priority Date: 06/28/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Oh, Chang-Woo
• Application Number:
  US12/687,286
• Publication Number:
  US 20100117152A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a first isolation dielectric pattern on the semiconductor substrate;

an active pattern on the first isolation dielectric pattern;

a semiconductor pattern between the semiconductor substrate and the first isolation dielectric pattern;

a second isolation dielectric pattern between the semiconductor substrate and the semiconductor pattern; and

a connection pattern connecting the semiconductor substrate and the semiconductor pattern.

2. The semiconductor device of claim 1, further comprising a gate dielectric and a gate electrode that are sequentially stacked on the active pattern,

wherein a depletion layer is generated in the active pattern and the semiconductor pattern when the semiconductor device operates.

3. The semiconductor device of claim 2, wherein the depletion layer is expanded into the semiconductor substrate.

4. The semiconductor device of claim 1, wherein the connection pattern contacts a side surface of the semiconductor pattern and the semiconductor substrate of a one side of the semiconductor pattern.

5. The semiconductor device of claim 1, wherein the second isolation dielectric pattern comprises the same insulating material as the first isolation dielectric pattern.

6. The semiconductor device of claim 1, wherein the semiconductor substrate and the semiconductor pattern are electrically connected by the connection pattern.

7. The semiconductor device of claim 1, wherein the gate electrode is extended onto a side wall of the active pattern, and

the first isolation dielectric pattern is extended between the gate electrode and the active pattern.

8. The semiconductor device of claim 1, wherein a channel region in the active pattern comprises an undoped semiconductor material, and

the semiconductor pattern comprises a doped semiconductor material.

9. The semiconductor device of claim 1, wherein the connection pattern comprises a semiconductor material and/or a conductive material.

10. The semiconductor device of claim 9, wherein the connection pattern and the semiconductor pattern comprise the same material.

11-19. -19. (canceled)