Interface structure of wafer test equipment

• US 20100117673A1
• Filed: 06/02/2009
• Published: 05/13/2010
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-hoon, Ko, Chang-woo, Oh, Se-jang, An, Young-soo
• Granted Patent: US 8,026,733 B2
• Time in Patent Office: Days
• US Class Current: 324/756.30
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

A wafer test equipment system includes a performance board connected to a tester head of a tester. A universal block printed circuit board is positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card. A cable assembly transfers the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head. The cable assembly is soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board. A probe card is removably secured to the performance board including the universal block printed circuit board. The probe card includes an interposer on an upper surface thereof, a ceramic multi-layer substrate positioned below the interposer, and a plurality of needles positioned below the ceramic multi-layer substrate on a lower surface thereof opposite the upper surface.

Claims

1. A wafer test equipment system, comprising:

a performance board connected to a tester head of a tester;

a universal block printed circuit board positioned on the performance board, directly connecting a plurality of normal signal lines to a probe card and dividing each of a plurality of power signal lines into multiple paths and connecting them to the probe card;

a cable assembly transferring the normal signal lines and the power signal lines between the universal block printed circuit board and the tester head, the cable assembly soldered directly to the universal block printed circuit board in a perpendicular direction through a center portion of the performance board; and

a probe card that is removably secured to the performance board including the universal block printed circuit board, the probe card including an interposer on an upper surface thereof, a ceramic multi-layer substrate positioned below the interposer, and a plurality of needles positioned below the ceramic multi-layer substrate on a lower surface thereof opposite the upper surface.

2. The wafer test equipment system of claim 1, wherein the performance board and the probe card are electrically connected at a plurality of connection contact points at a lower surface of the universal block printed circuit board at a lower portion of the performance board, and wherein the connection contact points correspond with interposer terminals of the interposer of the probe card on the upper surface of the probe card.

3. The wafer test equipment system of claim 2, wherein the universal block printed circuit board has a matrix structure including a plurality of blocks of printed circuit patterns and wherein each block includes the connection contact points that are provided on the lower surfaces of the printed circuit patterns.

4. The wafer test equipment system of claim 2, wherein the normal signal lines and the connection contact points are directly connected to each other according to a 1:

1 signal transfer ratio, and wherein the power signal lines and the connection contact points are connected to each other according to a 1;

N signal transfer ratio, where N is a whole number greater than 1.

5. The wafer test equipment system of claim 1, wherein the probe card has a configuration that varies in accordance with the part type of a semiconductor device that is to be tested.

6. The wafer test equipment system of claim 1, wherein the performance board and the probe card are removably secured to each other via levers of a ZIF connector at an outer portion of the probe card that surrounds the interposer.

8. The wafer test equipment system of claim 1, wherein the power signal lines in the cable assembly are soldered directly to an upper surface of the universal printed circuit board of the performance board

9. The wafer test equipment system of claim 1, wherein the power signal lines in the cable assembly are connected to a conductive layer in a middle portion of the universal block printed circuit board.

10. The wafer test equipment system of claim 1, wherein the normal signal lines in the cable assembly are soldered directly to an upper surface of the universal printed circuit board of the performance board

11. The wafer test equipment system of claim 1, wherein the normal signal lines in the cable assembly are connected to a conductive layer in a middle portion of the universal block printed circuit board,

12. The wafer test equipment system of claim 1, wherein the normal signal lines in the cable assembly are connected through the universal block printed circuit board.

13. The wafer test equipment system of claim 1, wherein ground lines surround the outer portions of the power signal lines and the normal signal lines in the cable assembly, and are connected to ground conductive layers, respectively, formed on an upper surface and a lower surface of the universal block printed circuit board.

7. The wafer test equipment system of claim 7, wherein the probe card further comprises a support surrounding the ceramic multi-layer substrate;

and wherein the levers of the ZIF connector are positioned on the support.