SEMICONDUCTOR DEVICE

• US 20100117690A1
• Filed: 01/22/2010
• Published: 05/13/2010
• Est. Priority Date: 07/24/2007
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: DOI, Yoshiyasu
• Application Number:
  US12/692,185
• Publication Number:
  US 20100117690A1
• Time in Patent Office: Days
• US Class Current: 327/108
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A semiconductor device includes a first buffer circuit transmitting input signals, a second buffer circuit having a lower drive capability than the first buffer circuit and transmitting the input signals, and a control circuit detecting transitions of the input signals, and activating the first buffer circuit during a period when the input signals make the transitions.

Claims

1. A semiconductor device comprising:

a first buffer circuit transmitting input signals;

a second buffer circuit having a lower drive capability than the first buffer circuit and transmitting the input signals; and

a control circuit detecting transitions of the input signals, and activating the first buffer circuit during a period when the input signals make the transitions.

2. The semiconductor device according to claim 1, wherein

the control circuit enables a current supply from a current source held by the first buffer circuit during the period when the input signals make the transitions.

3. The semiconductor device according to claim 1, wherein

a load held by the second buffer circuit is N times (N>

1) of a load held by the first buffer circuit.

4. The semiconductor device according to claim 1, wherein

the control circuit activates the first buffer circuit when the transitions of the input signals are detected, and after the activation of the first buffer circuit, inactivates the first buffer circuit after an output signal reaches a definite voltage or after a definite period of time has passed.

5. The semiconductor device according to claim 1, wherein

the control circuit includes:

a signal transition detecting circuit detecting the transitions of the input signals; and

switching circuits being turned ON/OFF in accordance with a detection result by the signal transition detecting circuit and controlling a current supply to the first buffer circuit.

6. The semiconductor device according to claim 5, wherein

the signal transition detecting circuit is a high-pass filter or a band-pass filter.

7. The semiconductor device according to claim 1, wherein

the first buffer circuit and the second buffer circuit are coupled in parallel relative to the input signals.

8. The semiconductor device according to claim 1, wherein

the first buffer circuit and the second buffer circuit are constituted by one buffer circuit.

9. The semiconductor device according to claim 1, wherein

the first buffer circuit and the second buffer circuit commonly use at least a part of circuit elements constituting each buffer circuit.

10. The semiconductor device according to claim 1, wherein

the first buffer circuit is a circuit changing output signals in accordance with the transitions of the input signals, and

the second buffer circuit is a circuit maintaining amplitudes of the output signals.

11. The semiconductor device according to claim 1, wherein

the control circuit inactivates the second buffer circuit during a period when the input signals make the transitions.

12. The semiconductor device according to claim 1, wherein

the control circuit exclusively inactivates the first buffer circuit and the second buffer circuit in accordance with the detection result of the transitions of the input signals.

13. The semiconductor device according to claim 1, wherein

the first and second buffer circuits are constituted by using a differential pair.

14. The semiconductor device according to claim 1, wherein

the first buffer circuit is constituted by using an inverter, and the second buffer circuit is constituted by using a differential pair.

15. A semiconductor device, comprising:

a first and second buffer circuits coupled in parallel relative to input signals and transmitting the input signals, wherein

the first buffer circuit includes;

a first drive circuit to which the input signals are inputted;

a first load coupled to the first drive circuit via a first switching circuit; and

a first current source coupled to the first drive circuit via a second switching circuit, and

the second buffer circuit includes;

a second drive circuit of which drive capability is lower than the first drive circuit and to which the input signals are inputted;

a second load which is N times (N>

1) of the first load, and coupled to the second drive circuit; and

a second current source coupled to the second drive circuit, and wherein

the first and second switching circuits are ON/OFF controlled in accordance with a detection result of the transitions of the input signals.