Apparatus and method for analog-to-digital converter calibration

• US 20100117876A1
• Filed: 01/14/2010
• Published: 05/13/2010
• Est. Priority Date: 12/21/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Cao, Jun, Momtaz, Afshin
• Granted Patent: US 7,911,365 B2
• Time in Patent Office: Days
• US Class Current: 341/118
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/362 the reference values being generated by a resistive voltage divider

Abstract

An analog-to-digital converter (ADC) is provided. The ADC includes a reference voltage generator configured to generate reference voltages, an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits, and a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.

Claims

1. An analog-to-digital converter (ADC), comprising:

a reference voltage generator configured to generate reference voltages;

an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of the input signal, the digital signal having a number of bits; and

a controller configured to determine a quality of the input signal, and, based on a quality of the input signal, to control the number of bits of the digital signal and values of the reference voltages.

2. The ADC of claim 1, wherein the controller is configured to generate a precision control signal that controls the number of bits of the digital signal and the values of the reference voltages.

3. The ADC of claim 1, wherein the controller is configured to decrease the number of bits of the digital signal by cutting off power to a portion of the analog to digital converter core.

4. The ADC of claim 3, wherein the controller is configured to decrease the number of bits of the digital signal by one bit by cutting off power to substantially half of the analog to digital converter core.

5. The ADC of claim 3, wherein the analog to digital converter core includes a biasing element and wherein the controller is configured to cut off power to the portion of the analog to digital core by controlling a state of the biasing element.

6. The ADC of claim 5, wherein the biasing element comprises a diode.

7. The ADC of claim 1, wherein the controller is configured to determine the quality of the input signal based on a signal-to-noise ratio of the input signal or a likelihood of errors being present in the input signal.

8. The ADC of claim 1, wherein the reference voltage generator comprises a switch coupled to a current source, wherein the controller is configured to control the values of the reference voltages by controlling the state of the switch.

9. The ADC of claim 1, wherein the analog to digital converter core comprises a plurality of slices, each slice comprising:

a comparator configured to compare the analog input to a reference voltage and produce an output;

a digital to analog converter (DAC); and

a digital processing unit (DPU) that is electrically connected to the comparator and the DAC;

wherein the DPU is configured to sample the output of the comparator to infer information associated with a first offset and generate a signal from the inferred information and wherein the DAC is configured to receive the signal and generate a second offset that opposes the first offset.

10. The ADC of claim 9, wherein the controller is configured to power up or power down one or more DACs based on the quality of the input signal.

11. An analog to digital converter (ADC), comprising:

an analog to digital converter core configured to receive an input signal and reference voltages and to generate a digital signal representative of the input signal; and

a controller configured to transition the analog to digital converter core from a first state to a second state based on a quality of the input signal, wherein, in the first state, the analog to digital converter core has a first number of elements active and, in the second state, the analog to digital converter core has a second number of elements active and wherein the first number and the second number are different.

12. The ADC of claim 11, wherein the digital signal has a number of bits and wherein the number of bits of the digital signal is different in the first state than in the second state.

13. The ADC of claim 11, wherein the first number is substantially half of the second number.

14. An analog-to-digital converter (ADC), comprising:

means for generating reference voltages;

an analog to digital converter core configured to receive an input signal and the reference voltages and to generate a digital signal representative of an input signal, the digital signal having a number of bits; and

means for determining a quality of the input signal, and controlling, based on a quality of the input signal, the number of bits of the digital signal and values of the reference voltages.

15. The ADC of claim 14, wherein the means for controlling is configured to decrease the number of bits of the digital signal by cutting off power to a portion of the analog to digital converter core when the quality of the input signal increases.

16. The ADC of claim 14, wherein the analog to digital converter core comprises a plurality of slices, each slice comprising:

a comparator configured to compare the analog input to a reference voltage and produce an output;

a digital to analog converter (DAC); and

a digital processing unit (DPU) that is electrically connected to the comparator and the DAC;

wherein the DPU is configured to sample the output of the comparator to infer information associated with a first offset and generate a signal from the inferred information and wherein the DAC is configured to receive the signal and generate a second offset that opposes the first offset.

17. The ADC of claim 14, wherein the means for controlling is configured to power up or power down one or more DACs based on the quality of the input signal.

18. A method of analog to digital conversion, comprising:

determining a quality of an input signal, wherein an analog to digital converter core generates a digital signal representative of the input signal using reference voltages, the digital signal having a number of bits;

controlling the number of bits based on the determined quality; and

controlling values of the reference voltages based on the quality of the input signal.

19. The method of claim 18, wherein controlling the number of bits comprises:

generating a precision control signal based on the determined quality.

20. The method of claim 18, wherein controlling the number of bits comprises:

cutting off power to a portion of the analog to digital converter core.