LIQUID CRYSTAL DISPLAY DEVICE, LIQUID CRYSTAL DISPLAY DEVICE DRIVE METHOD, AND TELEVISION RECEIVER

• US 20100118013A1
• Filed: 03/27/2008
• Published: 05/13/2010
• Est. Priority Date: 06/12/2007
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kitayama, Masae, Irie, Kentaro, Yamada, Naoshi, Shimoshikiryoh, Fumikazu, Tsubata, Toshihide
• Granted Patent: US 8,451,205 B2
• Time in Patent Office: Days
• US Class Current: 345/211
• CPC Class Codes: G09G 2300/0443 with several sub-pixels for the same colour in a pixel, not specifically used to display gradations G09G3/364 takes precedence
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/028 by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

In one embodiment of the present invention, a gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period. This makes it possible to provide a liquid crystal display device capable of offering high quality display in which unevenness in the display is suppressed without being affected by the blunt waveform of the data signal and the blunt waveform of a retention volume signal at the time of the inversion.

Claims

1. An active-matrix liquid crystal display device, including:

scanning signal lines extending in a row direction;

data signal lines extending in a column direction;

retention capacitor lines extending in a row direction;

a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and

pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode,

the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively,

the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines,

the liquid crystal display device comprising;

a scanning signal driving section for sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state;

a data signal driving section for applying, on the data signal lines, data signals whose polarities are switched with predetermined timing; and

a retention capacitor signal driving section for applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing,

the data signal driving section providing a dummy insertion period right after a moment of polarity inversion of a data signal and causing a polarity of a data signal applied on a data signal line during the dummy insertion period to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and

the retention capacitor signal driving section causing polarity inversion timing of individual retention capacitor signals at least in an adjacent line writing time difference period to be equal among successive frames, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.

3. The liquid crystal display device as set forth in claim 1, wherein the data signal driving section provides a dummy insertion period right after a moment of polarity inversion of a data signal and causes a data signal applied on a data signal line during the dummy insertion period to be equal to a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.

4. The liquid crystal display device as set forth in claim 1, wherein the scanning signal driving section does not apply the gate-on pulse during the dummy insertion period.

5. The liquid crystal display device as set forth in claim 1, wherein

the number of the blocks of scanning signal lines is one, and

the data signal driving section applies the data signals on the data signal lines such that a polarity of a data signal is inverted at a moment of switching groups of scanning signal lines to be scanned.

6. The liquid crystal display device as set forth in claim 1, wherein

the number of the blocks of scanning signal lines is two or more, and

the data signal driving section applies the data signals on the data signal lines such that a polarity of a data signal is inverted at a moment of switching groups of scanning signal lines to be scanned.

7. The liquid crystal display device as set forth in claim 1, wherein a polarity inversion cycle of a retention capacitor signal is obtained by dividing the adjacent line writing time difference period by k (k is an integer of 1 or more).

8. The liquid crystal display device as set forth in claim 7, wherein k is 1.

9. The liquid crystal display device as set forth in claim 1, wherein also in a period other than the adjacent line writing time difference period, a polarity of a retention capacitor signal is periodically inverted with a polarity inversion cycle of the adjacent line writing time difference period.

10. The liquid crystal display device as set forth in claim 9, wherein a polarity continuation period of a retention capacitor signal during a period to which the dummy insertion period is inserted is longer by the dummy insertion period than a polarity continuation period of a retention capacitor signal during a period other than the period to which the dummy insertion period is inserted, the polarity continuation period being a period during which one polarity of a retention capacitor signal continues.

11. The liquid crystal display device as set forth in claim 9, wherein a polarity continuation period of a retention capacitor signal is either a polarity continuation period with a first length or a polarity continuation period with a second length that is a sum of the first length and a length of the dummy insertion period, the polarity continuation period being a period during which one polarity of a retention capacitor signal continues.

12. The liquid crystal display device as set forth in claim 9, wherein the retention capacitor signal driving section applies retention capacitor signals with a same phase on a plurality of retention capacitor signal supply lines.

13. The liquid crystal display device as set forth in claim 9, wherein when supplying a retention capacitor signal to retention capacitor lines to which retention capacitor signals with a same phase are applied, the retention capacitor signal driving section supplies the retention capacitor signal via one retention capacitor signal supply line.

14. The liquid crystal display device as set forth in claim 1, wherein the dummy insertion period is a multiple number of a horizontal period.

15. The liquid crystal display device as set forth in claim 14, wherein a phase of a retention capacitor signal to be applied on n+2^nd retention capacitor line is delayed by 1 horizontal period with respect to a phase of a retention capacitor signal to be applied on n^th retention capacitor line.

16. The liquid crystal display device as set forth in claim 14, wherein

the retention capacitor signal driving section generates m kinds of retention capacitor signals, drives two retention capacitor lines with one retention capacitor line therebetween with use of retention capacitor signals with a same phase, and regards at least one polarity continuation period as a (k×

m) horizontal period (k is an integer of 1 or more), and

a phase of a retention capacitor signal to be applied on (n+2(k+1))^th retention capacitor line is delayed by (k+1) horizontal period with respect to a phase of a retention capacitor signal to be applied on n^th retention capacitor line.

17. The liquid crystal display device as set forth in claim 9, wherein polarity continuation periods are equal with one another, each of the polarity continuation periods being a period in which a polarity of a retention capacitor signal continues.

18. The liquid crystal display device as set forth in claim 1, further comprising a display control circuit for supplying, to the data signal driving section, a data signal and a data signal application control signal for controlling timing with which the data signal driving section applies the data signal on a data signal line,

a plurality of video data that respectively correspond to data signal lines being sequentially supplied from an external signal source to the display control circuit with an interval between the plurality of video data, and

the display control circuit regards certain number of video data as a set in accordance with polarity inversion, inserts dummy data at a predetermined position of the set, assigns a dummy insertion period to an output of a signal potential corresponding to the dummy data, and assigns a horizontal period shorter than the interval to an output of a signal potential corresponding to each video data.

19. The liquid crystal display device as set forth in claim 18, wherein a product of the number of video data in a set and the interval is equal to a sum of a whole dummy insertion period assigned to dummy data in the set and a whole horizontal period assigned to the video data in the set.

20. The liquid crystal display device as set forth in claim 18, wherein the display control circuit inserts dummy data at a head of each set.

21. The liquid crystal display device as set forth in claim 1, further comprising a display control circuit for supplying, to the data signal driving section, a data signal and a data signal application control signal for controlling timing with which the data signal driving section applies the data signal on a data signal line,

a plurality of video data that respectively correspond to data signal lines being sequentially supplied from an external signal source to the display control circuit with an interval between the plurality of video data, and

the display control circuit regards certain number of video data as a set in accordance with polarity inversion, assigns one or more dummy insertion periods as well as one horizontal period to an output of a signal potential corresponding to predetermined video data in each set, and assigns a horizontal period shorter than the interval to outputs of signal potentials respectively corresponding to individual video data other than the predetermined video data in each set.

22. The liquid crystal display device as set forth in claim 21, wherein a product of the number of video data in each set and the interval is equal to a sum of a whole horizontal period assigned to the predetermined video data in each set, a whole dummy insertion period assigned to the predetermined video data in each set, and a whole horizontal period assigned to the individual video data other than the predetermined video data in each set.

23. The liquid crystal display device as set forth in claim 22, wherein the predetermined video data in each set is first data in each set.

24. The liquid crystal display device as set forth in claim 18, wherein the dummy insertion period is shorter than the interval.

25. The liquid crystal display device as set forth in claim 18, wherein the dummy insertion period is equal to one horizontal period.

26. The liquid crystal display device as set forth in claim 18, wherein the dummy insertion period is shorter than one horizontal period.

27. The liquid crystal display device as set forth in claim 18, wherein the dummy insertion period is longer than one horizontal period.

28. The liquid crystal display device as set forth in claim 21, wherein the dummy insertion period is shorter than the interval.

29. The liquid crystal display device as set forth in claim 21, wherein the dummy insertion period is equal to one horizontal period.

30. The liquid crystal display device as set forth in claim 21, wherein the dummy insertion period is shorter than one horizontal period.

31. The liquid crystal display device as set forth in claim 21, wherein the dummy insertion period is longer than one horizontal period.

32. The liquid crystal display device as set forth in claim 1, wherein the retention capacitor signal driving section provides, in a polarity continuation period of a retention capacitor signal, a period during which a first voltage is applied and a period during which a second voltage of a same polarity as the first voltage and with a larger absolute value than the first voltage is applied.

33. The liquid crystal display device as set forth in claim 32, wherein in accordance with a length of a polarity inversion cycle of a retention capacitor signal, the retention capacitor signal driving section changes at least one of the period in which the second voltage is applied and timing of applying the second voltage.

34. The liquid crystal display device as set forth in claim 12, wherein the number of scanning signal lines in one block is α

(α

is a natural number), a dummy insertion period is inserted at two or more positions while scanning one block, and the retention capacitor lines are driven in response to retention capacitor signals with at least α

/k (k is a natural number and α

/k is an integer)+2 phases.

35. The liquid crystal display device as set forth in claim 12, wherein the number of scanning signal lines in one block is α

(α

is a natural number), two retention capacitor lines with one retention capacitor line therebetween of first half α

/2 (α

/2 is a natural number) retention capacitor lines in each block are driven in response to retention capacitor signals with a same phase, and two retention capacitor lines with one retention capacitor line therebetween of second half α

/2 retention capacitor lines in each block are driven in response to retention capacitor signals with a same phase, so that all of the retention capacitor lines are driven in response to retention capacitor signals with at least α

/2k (k is an integer of 2 or more and α

/2k is an integer) phases.

36. The liquid crystal display device as set forth in claim 9, wherein during a period including a dummy insertion period, in which one block is scanned, a difference between a period in which a retention capacitor signal is in H level and a period in which the retention capacitor signal is in L level is equal to or less than 1 horizontal period.

37. The liquid crystal display device as set forth in claim 9, wherein during a period including a dummy insertion period, in which one block is scanned, a ratio of a difference between a period in which a retention capacitor signal is in H level and a period in which the retention capacitor signal is in L level to 1 frame period is equal to or less than 0.13%.

38. The liquid crystal display device as set forth in claim 9, wherein a difference among retention capacitor lines in an absolute value of a difference between H level period and L level period of a retention capacitor signal in one frame is equal to or less than 1 horizontal period.

39. The liquid crystal display device as set forth in claim 9, wherein a ratio of a difference among retention capacitor lines in an absolute value of a difference between H level period and L level period of a retention capacitor signal in one frame to one frame period is equal to or less than 0.13%.

43. A television receiver, comprising a liquid crystal display device as set forth in claim 1, and a tuner section for receiving television broadcasting.

2. An active-matrix liquid crystal display device, including:

scanning signal lines extending in a row direction;

data signal lines extending in a column direction;

retention capacitor lines extending in a row direction;

a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and

pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode,

the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively,

the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines,

the liquid crystal display device comprising;

a scanning signal driving section for sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state;

a data signal driving section for applying, on the data signal lines, data signals whose polarities are switched with predetermined liming; and

a retention capacitor signal driving section for applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing,

the data signal driving section providing a dummy insertion period right after a moment of polarity inversion of a data signal and causing a polarity of a data signal applied on a data signal line during the dummy insertion period to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and

the retention capacitor signal driving section causing polarity inversion cycles of all of the retention capacitor signals to be equal at least in an adjacent line writing time difference period, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.

44. The liquid crystal display device as set forth in claim 2, wherein the data signal driving section provides a dummy insertion period right after a moment of polarity inversion of a data signal and causes a data signal applied on a data signal line during the dummy insertion period to be equal to a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.

45. The liquid crystal display device as set forth in claim 2, wherein the scanning signal driving section does not apply the gate-on pulse during the dummy insertion period.

46. The liquid crystal display device as set forth in claim 2, wherein

the number of the blocks of scanning signal lines is one, and

the data signal driving section applies the data signals on the data signal lines such that a polarity of a data signal is inverted at a moment of switching groups of scanning signal lines to be scanned.

47. The liquid crystal display device as set forth in claim 2, wherein

the number of the blocks of scanning signal lines is two or more, and

the data signal driving section applies the data signals on the data signal lines such that a polarity of a data signal is inverted at a moment of switching groups of scanning signal lines to be scanned.

48. The liquid crystal display device as set forth in claim 2, wherein a polarity inversion cycle of a retention capacitor signal is obtained by dividing the adjacent line writing time difference period by k (k is an integer of 1 or more).

49. The liquid crystal display device as set forth in claim 2, wherein also in a period other than the adjacent line writing time difference period, a polarity of a retention capacitor signal is periodically inverted with a polarity inversion cycle of the adjacent line writing time difference period.

50. The liquid crystal display device as set forth in claim 2, wherein the dummy insertion period is a multiple number of a horizontal period.

51. The liquid crystal display device as set forth in claim 2, further comprising a display control circuit for supplying, to the data signal driving section, a data signal and a data signal application control signal for controlling timing with which the data signal driving section applies the data signal on a data signal line,

a plurality of video data that respectively correspond to data signal lines being sequentially supplied from an external signal source to the display control circuit with an interval between the plurality of video data, and

the display control circuit regards certain number of video data as a set in accordance with polarity inversion, inserts dummy data at a predetermined position of the set, assigns a dummy insertion period to an output of a signal potential corresponding to the dummy data, and assigns a horizontal period shorter than the interval to an output of a signal potential corresponding to each video data.

52. The liquid crystal display device as set forth in claim 2, further comprising a display control circuit for supplying, to the data signal driving section, a data signal and a data signal application control signal for controlling timing with which the data signal driving section applies the data signal on a data signal line,

a plurality of video data that respectively correspond to data signal lines being sequentially supplied from an external signal source to the display control circuit with an interval between the plurality of video data, and

the display control circuit regards certain number of video data as a set in accordance with polarity inversion, assigns one or more dummy insertion periods as well as one horizontal period to an output of a signal potential corresponding to predetermined video data in each set, and assigns a horizontal period shorter than the interval to outputs of signal potentials respectively corresponding to individual video data other than the predetermined video data in each set.

53. The liquid crystal display device as set forth in claim 2, wherein the retention capacitor signal driving section provides, in a polarity continuation period of a retention capacitor signal, a period during which a first voltage is applied and a period during which a second voltage of a same polarity as the first voltage and with a larger absolute value than the first voltage is applied.

55. A television receiver, comprising a liquid crystal display device as set forth in claim 2, and a tuner section for receiving television broadcasting.

40. A method for driving an active-matrix liquid crystal display device, including:

scanning signal lines extending in a row direction;

data signal lines extending in a column direction;

retention capacitor lines extending in a row direction;

a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and

pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode,

the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively,

the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines,

the method comprising;

(i) sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state;

(ii) applying, on the data signal lines, data signals whose polarities are switched with predetermined timing; and

(iii) applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing,

in the step (ii), a dummy insertion period being provided right after a moment of polarity inversion of a data signal and a polarity of a data signal applied on a data signal line during the dummy insertion period being caused to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and

in the step (iii), polarity inversion timing of individual retention capacitor signals at least in an adjacent line writing time difference period being caused to be equal among successive frames, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.

42. The method as set forth in claim 40, wherein in the step (ii), a dummy insertion period is provided right after a moment of polarity inversion of a data signal and a data signal applied on a data signal line during the dummy insertion period is caused to be equal to a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.

41. A method for driving an active-matrix liquid crystal display device, including:

scanning signal lines extending in a row direction;

data signal lines extending in a column direction;

retention capacitor lines extending in a row direction;

a first transistor and a second transistor that are provided near each of intersections of the scanning signal lines and the data signal lines and that are connected with each of the scanning signal lines and each of the data signal lines; and

pixel regions each including a first sub-pixel electrode and a second sub-pixel electrode,

the first sub-pixel electrode being connected with the first transistor and the second sub-pixel electrode being connected with the second transistor, the first sub-pixel electrode and the second sub-pixel electrode being connected with different ones of the retention capacitor lines to form retention capacitors, respectively,

the scanning signal lines being divided into one or more blocks, and scanning signal lines included in each block being divided into a first group consisting of odd scanning signal lines and a second group consisting of even scanning signal lines,

the method comprising;

(i) sequentially scanning blocks of scanning signal lines and sequentially scanning groups of scanning signal lines in each block such that the scanning signal lines in each block are interlace-scanned, so as to sequentially apply gate-on pulses on the scanning signal lines, each of the gate-on pulses causing one of the scanning signal lines to be in a selected state;

(ii) applying, on the data signal lines, data signals whose polarities are switched with predetermined liming; and

(iii) applying, on the retention capacitor lines, retention capacitor signals whose polarities are switched with predetermined timing,

in the step (ii), a dummy insertion period being provided right after a moment of polarity inversion of a data signal and a polarity of a data signal applied on a data signal line during the dummy insertion period being caused to be equal to a polarity of a data signal applied on the data signal line during a horizontal period right after the dummy insertion period, and

in the step (iii), polarity inversion cycles of all of the retention capacitor signals being caused to be equal at least in an adjacent line writing time difference period, the adjacent line writing time difference period being a period from a moment of application of a gate-on pulse on a scanning signal line that is one of adjacent two scanning signal lines and that belongs to a first group or a second group firstly subjected to application of a gate-on pulse to a moment of application of a gate-on pulse on a scanning signal line that is the other of the adjacent two scanning signal lines and that belongs to a second group or a first group secondly subjected to application of a gate-on pulse.

54. The method as set forth in claim 41, wherein in the step (ii), a dummy insertion period is provided right after a moment of polarity inversion of a data signal and a data signal applied on a data signal line during the dummy insertion period is caused to be equal to a data signal applied on the data signal line during a horizontal period right after the dummy insertion period.