DIFFERENTIAL TIMING TRANSFER OVER SYNCHRONOUS ETHERNET USING DIGITAL FREQUENCY GENERATORS AND CONTROL WORD SIGNALING

• US 20100118894A1
• Filed: 11/10/2008
• Published: 05/13/2010
• Est. Priority Date: 11/10/2008
• Status: Active Grant

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: MONTUNO, Delfin Y., AWEYA, James, OUELLETTE, Michel
• Granted Patent: US 8,467,418 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 1/0328 in which the phase increment is adjustable, e.g. by using an adder-accumulator
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04L 7/0079 Receiver details

Abstract

A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Claims

1. A method for transferring differential timing over a packet network, the packet network having a transmitting service interface coupled to a receiving service interface through a network backplane, the method comprising:

providing a primary reference clock to time the network backplane;

using the primary reference clock and a service clock connected to the transmitting service interface to synthesize a copy of the service clock;

generating a first control word containing an error differential between the service clock and the synthesized copy of the service clock;

transmitting a packet containing the first control word through the network backplane to the receiving service interface; and

using the first control word and the primary reference clock to recreate the service clock for timing the receiving service interface.

2. The method of claim 1, wherein the network backplane operates using a Synchronous Ethernet protocol.

3. The method of claim 1, wherein a frequency of the primary reference clock is supplied by one of a global positioning system and a building integrated timing supply.

4. The method of claim 1, wherein the transmitting service interface and the receiving service interface have dissimilar digital oscillators, the method further comprising mapping the first control word into a second control word usable by the digital oscillator of the receiving service interface.

5. The method of claim 1, further comprising:

updating the first control word at a periodic interval;

transmitting a packet containing the updated control word to the receiving service interface; and

applying the updated control word to the service clock timing the receiving service interface.

6. The method of claim 1, wherein the transmitting service interface includes a digital phase-locked loop, the digital phase-locked loop is synthesized from a specification for an analog phase-locked loop based on the digitization of a continuous-time system to a corresponding discrete-time system using a modified matched pole-zero method.

7. The method of claim 6, wherein the modified matched pole-zero method comprises:

mapping s-plane poles and zeros of the analog phase-locked loop into z-plane poles and zeros;

forming a discrete-time transfer function using the z-plane poles and zeroes; and

setting a low-frequency gain of the discrete-time system substantially equal to that of the continuous-time system.

8. A system for transferring differential timing over a packet network, the system comprising:

a network backplane timed by a primary reference clock;

a transmitting service interface communicatively coupled to the network backplane, the transmitting service interface connected to a service clock, the transmitting service interface operating to;

synthesize a copy of the service clock using the primary reference clock and the service clock;

generate a first control word containing an error differential between the service clock and the synthesized copy of the service clock; and

transmit a packet containing the first control word through the network backplane; and

a receiving service interface communicatively coupled to the network backplane, the receiving service interface operating to;

receive the first control word; and

use the first control word and the primary reference clock to recreate the service clock for timing the receiving service interface.

9. The system of claim 8, wherein a nominal control word is known by the receiving service interface, the first control word includes at least one correlation sample.

10. The system of claim 8, wherein a frequency of the primary reference clock is supplied by one of a global positioning system and a building integrated timing supply.

11. The system of claim 8, wherein the transmitting service interface and the receiving service interface have dissimilar digital oscillators, the receiving service interface further operates to map the first control word into a second control word usable by the digital oscillator of the receiving service interface.

12. The system of claim 8, wherein the transmitting service interface further operates to:

update the first control word at a periodic interval; and

transmit a packet containing the updated control word to the receiving service interface.

13. The system of claim 12, wherein the receiving service interface further operates to apply the updated control word to the service clock timing the receiving service interface.

14. The system of claim 8, wherein

the transmitting service interface includes a digital phase-locked loop, the digital phase-locked loop containing a phase-frequency detector, a loop filter and a master digital oscillator;

and

the receiving service interface includes a slave digital oscillator.

15. The system of claim 14, wherein the master digital oscillator is one of a direct digital synthesizer and a divide-by-N counter oscillator.

16. The system of claim 15, wherein the first control word is used to control the master digital oscillator and the slave digital oscillator.

17. The system of claim 14, wherein the digital phase-locked loop is synthesized from a specification for an analog phase-locked loop based on the digitization of a continuous-time system to a corresponding discrete-time system using a modified matched pole-zero method.

18. The system of claim 17, wherein the modified matched pole-zero method comprises:

mapping s-plane poles and zeros of the analog phase-locked loop into z-plane poles and zeros;

forming a discrete-time transfer function using the z-plane poles and zeroes; and

setting a low-frequency gain of the discrete-time system equal to that of the continuous-time system.

19. A master service interface for transferring differential timing over a packet network, the packet network being timed by a primary reference clock, the master service interface comprising:

a service clock operating to time the master service interface;

a master clock operating to;

synthesize a copy of the service clock using the primary reference clock and the service clock; and

generate a control word containing an error differential between the service clock and the synthesized copy of the service clock; and

a processor communicatively coupled to the master clock, the processor operating to transmit a packet containing the control word through the packet network.

20. The master service interface of claim 19, wherein the processor further operates to:

update the control word at a periodic interval; and

transmit a packet containing the updated control word to a slave service interface.