OPTOELECTRONIC DEVICE STRUCTURE

• US 20100120184A1
• Filed: 11/12/2009
• Published: 05/13/2010
• Est. Priority Date: 11/13/2008
• Status: Abandoned Application

• Current Assignee: Epistar Corporation (Ennostar, Inc.)
• Original Assignee: Epistar Corporation (Ennostar, Inc.)
• Inventors: Hsu, Chia-Liang, HUANG, Chien-Fu
• Application Number:
  US12/617,413
• Publication Number:
  US 20100120184A1
• Time in Patent Office: Days
• US Class Current: 438/29
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 2933/0058 relating to optical field-shaping elements
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 2933/0075 relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements
• CPC Class Codes: H01L 33/641 characterized by the materials

Abstract

The application is related to an optoelectronic device structure including a stress-balancing layer. The optoelectronic device structure comprises a high thermal conductive substrate, a stress-balancing layer on the high thermal conductive substrate, a reflective layer on the stress-balancing layer and an epitaxial structure on the reflective layer.

Claims

1. A method for forming an optoelectronic device comprising the steps of:

providing a growth substrate having a first surface and a second surface;

forming an epitaxial structure on the first surface of the growth substrate wherein the epitaxial structure comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;

forming a reflective layer on the epitaxial structure;

forming a stress-balancing layer by an electro chemical deposition process or an electroless chemical deposition process on a side of the reflective layer opposite to the epitaxial structure;

forming a high thermal conductive substrate by an electro chemical deposition process or an electroless chemical deposition process on a side of the stress-balancing layer opposite to the epitaxial structure wherein the stress-balancing layer can reduce the internal stress between the high thermal conductive substrate and the epitaxial structure, and the difference of the thermal expansion coefficients between the high thermal conductive substrate and the epitaxial structure is not smaller than 5 ppm/°

C.;

removing the growth substrate to expose a surface of the epitaxial structure;

forming an electrode on the exposed surface of the epitaxial structure wherein the electrode electrically connected to the epitaxial structure;

forming a plurality of channels by etching from the epitaxial structure to the high thermal conductive substrate; and

dicing along the plurality of channels.

2. The method according to claim 1, wherein the electro chemical deposition process for forming the stress-balancing layer is electro-plating or electroform.

3. The method according to claim 1, wherein the electroless chemical deposition process for forming the stress-balancing layer is electroless plating.

4. The method according to claim 1, wherein the electro chemical deposition process for forming the high thermal conductive substrate is electro-plating or electroform.

5. The method according to claim 1, wherein the electroless chemical deposition process for forming the high thermal conductive substrate is electroless plating.

6. The method according to claim 1, wherein the step for forming the plurality of channels further comprising photolithography process.

7. A method for forming an optoelectronic device comprising the steps of:

providing a growth substrate having a first surface and a second surface;

forming an epitaxial structure on the first surface of the growth substrate wherein the epitaxial structure comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;

forming a reflective layer on the epitaxial structure;

forming a stress-balancing layer by an electro chemical deposition process or an electroless chemical deposition process on a side of the reflective layer opposite to the epitaxial structure;

forming a regularly patterned structure on the stress-balancing layer by etching process wherein the width of each pattern of the regularly patterned structure of the stress-balancing layer is not smaller than 0.01 time and not greater than 1 time that of the optoelectronic device;

forming a high thermal conductive substrate by an electro chemical deposition process or an electroless chemical deposition process on a side of the stress-balancing layer opposite to the epitaxial structure wherein the stress-balancing layer with a regularly patterned structure can reduce the internal stress between the high thermal conductive substrate and the epitaxial structure;

removing the growth substrate to expose a surface of the epitaxial structure;

forming an electrode on the exposed surface of the epitaxial structure wherein the electrode electrically connected to the epitaxial structure;

forming a plurality of channels by etching from the epitaxial structure to the high thermal conductive substrate; and

dicing along the plurality of channels.

8. The method according to claim 7, wherein the electro chemical deposition process for forming the stress-balancing layer is electro-plating or electroform.

9. The method according to claim 7, wherein the electroless chemical deposition process for forming the stress-balancing layer is electroless plating.

10. The method according to claim 7, wherein the electro chemical deposition process for forming the high thermal conductive substrate is electro-plating or electroform.

11. The method according to claim 7, wherein the electroless chemical deposition process for forming the high thermal conductive substrate is electroless plating.

12. The method according to claim 7, wherein the step for forming the plurality of channels further comprising photolithography process.

13. A method for forming an optoelectronic device comprising the steps of:

providing a growth substrate having a first surface and a second surface;

forming an epitaxial structure on the first surface of the growth substrate wherein the epitaxial structure comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;

forming a reflective layer on the epitaxial structure;

forming a stress-balancing layer by an electro chemical deposition process or an electroless chemical deposition process on a side of the reflective layer opposite to the epitaxial structure;

forming a photoresist structure with a plurality of intervals under the stress-balancing layer;

forming a high thermal conductive substrate by an electro chemical deposition process or an electroless chemical deposition process between the photoresist structure under the stress-balancing layer, wherein the width of the high thermal conductive substrate is smaller than that of stress-balancing layer, and the stress-balancing layer can reduce the internal stress between the high thermal conductive substrate and the epitaxial structure;

removing the photoresist structure under the stress-balancing layer;

removing the growth substrate to expose a surface of the epitaxial structure;

forming an electrode on the exposed surface of the epitaxial structure, wherein the electrode electrically connected to the epitaxial structure;

forming a plurality of channels by etching from the epitaxial structure to the high thermal conductive substrate; and

dicing the plurality of channels.

14. The method according to claim 13, wherein the electro chemical deposition process for forming the stress-balancing layer is electro-plating or electroform.

15. The method according to claim 13, wherein the electroless chemical deposition process for forming the stress-balancing layer is electroless plating.

16. The method according to claim 13, wherein the electro chemical deposition process for forming the high thermal conductive substrate is electro-plating or electroform.

17. The method according to claim 13, wherein the electroless chemical deposition process for forming the high thermal conductive substrate is electroless plating.

18. The method according to claim 13, wherein the step for forming the plurality of channels further comprising photolithography process.