Embedded DRAM with multiple gate oxide thicknesses

• US 20100120213A1
• Filed: 11/13/2008
• Published: 05/13/2010
• Est. Priority Date: 11/13/2008
• Status: Active Grant

• Current Assignee: Mosys Incorporated (Peraso, Inc.)
• Original Assignee: Mosys Incorporated (Peraso, Inc.)
• Inventors: Choi, Jeong Y.
• Granted Patent: US 8,361,863 B2
• Time in Patent Office: Days
• US Class Current: 438/241
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells.

Claims

1. A method of forming a DRAM cell having an access transistor and a capacitor structure, the method comprising:

forming a field dielectric in a semiconductor substrate having a first conductivity type, wherein the field dielectric extends below an upper surface of the semiconductor substrate;

providing a first mask on an upper surface of the semiconductor substrate thereby exposing a capacitor region;

ion implanting an impurity into a first portion of the semiconductor substrate;

removing the first mask;

providing a second mask on the upper surface of the semiconductor substrate to expose the capacitor region and a logic transistor;

removing oxide portions of the capacitor region and logic transistor;

removing the second mask; and

forming an oxide layer on the upper surface of the semiconductor substrate to produce an oxide layer in the capacitor region that is greater in thickness than an oxide of the logic transistor, and less than the thickness of an oxide of the access transistor.

2. The method of claim 1, wherein said impurity is a dopant of a second conductivity type opposite the first conductivity.

3. A method of forming a dynamic random access memory (DRAM) cell in a semiconductor substrate comprising:

fabricating a storage capacitor of the DRAM cell with a thin gate dielectric layer; and

fabricating an access transistor of the DRAM cell with a thicker dielectric layer having a thickness greater than the thin gate dielectric layer, wherein a dopant is selectively implanted in an area that will constitute the storage capacitor to form the thin gate dielectric layer.

4. The method of claim 3, wherein the thin gate dielectric layer has a thickness in the range of about 28-35 Angstroms, and the thick dielectric layer has a thickness of about 50 Angstroms or greater.

5. The method of claim 3, wherein the thick dielectric layer is at least about 60 percent thicker than the thin gate dielectric layer.

6. The method of claim 3, wherein the dopant that is implanted is neither a source nor a drain region.

7. The method of claim 6, wherein the dopant implant is an oxidation enhancing implant that is performed prior to forming any type of conductive layers on the semiconductor substrate.

8. The method of claim 7, wherein the oxidation enhancing dopant is implanted at a dosage of 2×

10¹⁴/cm² to 1×

10¹⁵/cm².

9. A method of manufacturing an embedded DRAM memory that includes a memory area and a logic area on a semiconductor substrate comprising:

growing an oxide layer above the memory area and the logic area of the semiconductor substrate;

forming a first mask on an upper surface of the semiconductor substrate to expose a capacitor region within the memory area;

ion implanting a first dopant into the upper surface of the semiconductor substrate in the capacitor region;

removing the mask from the upper surface of the semiconductor substrate; and

growing a dielectric layer on the upper surface of the semiconductor substrate thereby forming an oxide layer on the capacitor that is thicker than a gate oxide in the logic area.

10. The method of claim 9, further comprising:

disposing a second mask that exposes the capacitor region and logic area;

removing the oxide layers in the capacitor region and the logic area; and

then

thermally oxidizing the semiconductor substrate to form the thin gate dielectric of the capacitor region while forming a gate dielectric for the logic area, wherein the thin gate dielectric of the capacitor region is thicker than the gate dielectric of the logic area.

11. The method of manufacturing the embedded DRAM memory of claim 9, wherein the second mask covers I/O circuitry of the embedded DRAM memory.

12. The method of claim 9, wherein the second mask covers both logic circuitry and I/O circuitry within the semiconductor substrate.

13. The method of claim 9, further comprising ion implanting into the semiconductor substrate a second dopant of opposite conductivity to said first dopant.

14. The method of claim 13, wherein said second dopant is implanted at a dosage of between 1×

10¹³ to 5×

10¹⁴ cm<sup>−

2</sup>.

15. The method of claim 9, further comprising forming shallow trench isolation regions within said substrate.

16. A method of forming an embedded DRAM memory, the method comprising:

forming shallow trench isolation regions in a well of a first conductivity type in a semiconductor substrate;

implanting dopant into a capacitor region of the semiconductor substrate;

growing a first dielectric layer on the substrate;

disposing a mask above an I/O region of the substrate leaving a portion of the first dielectric layer exposed;

removing at least a portion of the exposed dielectric layer;

providing a second dielectric layer on exposed regions of the substrate to produce an embedded memory having oxide regions of variable thicknesses.

17. The method of claim 16, wherein said removing step comprises removing the dielectric layer that is located outside said shallow trench isolation regions.

18. The method of claim 16, wherein the DRAM cell further includes an access transistor, and a logic area, wherein the gate oxide of the access transistor is substantially equivalent in thickness to the gate oxide of the logic area, and wherein the capacitor has a dielectric region having a thickness that exceeds the thickness of the gate oxide of the logic area and the gate oxide of the access transistor.

19. A method of forming an embedded DRAM system including DRAM cells and logic transistors on the same semiconductor substrate, each of the DRAM cells having an access transistor and a capacitor structure, the method comprising:

forming a first cavity in a first region of the semiconductor substrate;

forming a second cavity in a second region of the semiconductor substrate;

forming a first dielectric region in the first cavity and a second dielectric region in the second cavity;

etching a portion of the second dielectric region to create a recess that exposes a sidewall of the second cavity;

selectively implanting an oxidation enhancing dopant into the semiconductor substrate;

simultaneously forming a dielectric layer for the access transistor and the capacitor structure, wherein the dielectric layer of the capacitor structure has a different thickness than the thickness of the dielectric layer of the access transistor.

20. The method of claim 19, wherein the first and second cavity is formed by etching through openings of a first mask into the semiconductor substrate.

21. The method of claim 19, wherein said first cavity is defined by a trench having a first and a second depth.

22. The method of claim 20, wherein a second mask is provided to control the implantation of the dopant into a first and a second portion of the substrate.

23. The method of claim 22, wherein the second mask is modified by etching a portion of the mask to produce a thin end portion, wherein the dopant implant into the substrate covered by said thin end portion is restricted to a shallow depth.

24. The method of claim 22, wherein the dopant is implanted at an angle of less than 90 degrees relative to an axis perpendicular to the horizontal surface of the semiconductor substrate.

25. The method of claim 24, further comprising forming an electrode layer over the first dielectric layer and the second dielectric layer;

and patterning the electrode layer to form a capacitor electrode of the capacitor structure and a gate electrode of the access transistor, wherein the capacitor electrode extends over the upper surface of the semiconductor substrate and the sidewall of the second cavity such that the capacitor electrode is at least partially located in the recess of the second cavity.

26. The method of claim 25, wherein the oxidation enhancing dopant is implanted at a dosage of 2×

10¹⁴/cm² to 1×

10¹⁵/cm².

27. The method of claim 19 further comprising providing a photoresist that covers said first mask and part of the first cavity, thereby exposing a cavity portion of said first cavity to allow etching of the exposed cavity portion to a depth that is greater than the depth of an unexposed cavity portion.

28. A method of forming an embedded DRAM system including DRAM cells and logic transistors on a semiconductor substrate, each of the DRAM cells having an access transistor and a capacitor structure, the method comprising:

forming shallow trench isolation regions in the semiconductor substrate;

disposing a first mask on the semiconductor substrate to expose a capacitor region;

implanting a first dopant into the capacitor region;

removing the first mask;

growing a first oxide layer;

disposing a second mask, said second mask protecting at least a gate oxide region of the access transistor;

removing the first oxide layer in areas exposed by the second mask;

stripping the second mask; and

then

simultaneously forming a gate oxide for the logic transistor and a dielectric region for the capacitor structure, wherein the dielectric region of the capacitor structure has a different thickness than the thickness of the gate oxide of the access transistor.

29. The method of claim 28, further comprising forming a sacrificial oxide layer on the semiconductor substrate prior to disposing the first mask, said sacrificial oxide layer being removed after implanting of dopant into the capacitor region.

30. The method of claim 28, wherein the oxide region of the access transistor is formed in two oxidation steps.

31. The method of claim 28 wherein said second mask further protects an oxide region of an I/O transistor to enable a gate oxide for the I/O transistor to be formed in two oxidation steps.

32. The method of claim 28, further comprising ion implanting a second dopant of opposite conductivity to said first dopant.

33. The method of claim 32, wherein said second dopant is implanted at a dosage of between 1×

10¹³ to 5×

10¹⁴ cm².