METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20100120226A1
• Filed: 01/25/2010
• Published: 05/13/2010
• Est. Priority Date: 03/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kawamata, Ikuko, Arai, Yasuyuki, Yamazaki, Shunpei
• Granted Patent: US 7,811,884 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.

Claims

1. A method for manufacturing a nonvolatile semiconductor memory device comprising:

irradiating a single crystal semiconductor substrate with at least one of hydrogen and rare gas ions to form a single crystal semiconductor layer and a separation layer under the single crystal semiconductor layer, wherein the separation layer is formed at a certain depth from a surface of the single crystal semiconductor substrate;

selectively etching the single crystal semiconductor layer and the separation layer to form a groove in the single crystal semiconductor substrate so as to divide the single crystal semiconductor layer into a first single crystal semiconductor layer and a second single crystal semiconductor layer;

bonding a base substrate having an insulating surface and the first single crystal semiconductor layer with each other;

separating the first single crystal semiconductor layer from the single crystal semiconductor substrate so as to leave the first single crystal semiconductor layer over the insulating surface of the base substrate;

selectively etching the first single crystal semiconductor layer to divide into a third single crystal semiconductor layer and a fourth single crystal semiconductor layer;

forming a charge accumulation layer over the third single crystal semiconductor layer with a first insulating film interposed therebetween, wherein the charge accumulation layer covers a top face and part of side faces of the third single crystal semiconductor layer with the first insulating film interposed therebetween, and

forming a control gate electrode layer over the floating gate and a gate electrode layer over the fourth single crystal semiconductor layer, respectively with a second insulating film interposed therebetween.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the third single crystal semiconductor layer is different from the fourth single crystal semiconductor layer in size.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the separating step is conducted by a heat treatment.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the single crystal semiconductor substrate comprises single crystal silicon.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the base substrate comprises single crystal silicon.

6. A method for manufacturing a nonvolatile semiconductor memory device comprising:

forming a silicon oxide film on a single crystal semiconductor substrate;

forming a first insulating film on the silicon oxide film;

irradiating the single crystal semiconductor substrate with at least one of hydrogen and rare gas ions to form a single crystal semiconductor layer and a separation layer under the single crystal semiconductor layer, wherein the separation layer is formed at a certain depth from a surface of the single crystal semiconductor substrate;

selectively etching the single crystal semiconductor layer to form a groove in the single crystal semiconductor substrate so as to divide the single crystal semiconductor layer into a first single crystal semiconductor layer and a second single crystal semiconductor layer, wherein the first single crystal semiconductor layer has a silicon oxide layer on it;

bonding a base substrate having an insulating surface and the first single crystal semiconductor layer interposed with the silicon oxide layer therebetween;

separating the first single crystal semiconductor layer from the single crystal semiconductor substrate so as to leave the first single crystal semiconductor layer over the insulating surface of the base substrate with the silicon oxide layer therebetween;

selectively etching the first single crystal semiconductor layer to divide into a third single crystal semiconductor layer and a fourth single crystal semiconductor layer;

forming a charge accumulation layer over the third single crystal semiconductor layer with a second insulating film interposed therebetween, wherein the charge accumulation layer covers a top face and part of side faces of the third single crystal semiconductor layer with the first insulating film interposed therebetween, and

forming a control gate electrode layer over the floating gate and a gate electrode layer over the fourth single crystal semiconductor layer, respectively with a third insulating film interposed therebetween.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the third single crystal semiconductor layer is different from the fourth single crystal semiconductor layer in size.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the separating step is conducted by a heat treatment.

9. The method for manufacturing a semiconductor device according to claim 6, wherein the single crystal semiconductor substrate comprises single crystal silicon.

10. The method for manufacturing a semiconductor device according to claim 6, wherein the base substrate comprises single crystal silicon.