Method for processing data using triple buffering

• US 20100122045A1
• Filed: 11/09/2009
• Published: 05/13/2010
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: Thomson Licensing (Vantiva SA)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Huetter, Ingo
• Granted Patent: US 8,359,446 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

The present invention relates to a method for processing data. A data block to be processed is written to a memory area in a first interval of time. The data block is processed in the same memory area (A, B, C) in a second interval of time. The processed data block is returned from the same memory area in a third interval of time.

Claims

1. Method for processing data, a data block to be processed

being written to a memory area in a first interval of time, and

being processed in the same memory area in a second interval of time,

the processed data block is transferred from the same memory area in a third interval of time

three memory areas in the memory are grouped to form a group of memory areas,

one or more groups of memory areas are used for the method, and

one memory area in a group of memory areas is respectively used to receive, process and transfer data in each interval of time.

2. Method according to claim 1, wherein the method is used for image processing.

3. Method according to claim 1, wherein an algorithm which does not randomly access data which have already been processed is executed during the step of processing a data block.

4. Method according to claim 1, wherein data from a first data processing system are processed in a second data processing system, a data block to be processed

being written to a memory area of the second data processing system in a first interval of time,

being processed in the same memory area of the second data processing system in a second interval of time, and

being returned to the first data processing system from this memory area of the second data processing system in a third interval of time.

5. Method according to claim 4, wherein the second data processing system is a subsystem of the first data processing system.

6. Method according to claim 4, wherein the first data processing system is a central processing unit and the second data processing system is a coprocessor.

7. Method according to claim 1, wherein the first data processing system is a PowerPC processor element and the second data processing system is a synergistic processor element.

8. Data processing system for carrying out a method according to claim 1.

9. Method for processing data, a data block to be processed

being written to a memory area in a first interval of time, and

being processed in the same memory area in a second interval of time,

the processed data block is transferred from the same memory area in a third interval of time, wherein

an algorithm which does not randomly access data which have already been processed is executed during the step of processing a data block.

10. Method according to claim 9, wherein three memory areas in the memory are grouped to form a group of memory areas.

11. Method according to claim 10, wherein

one or more groups of memory areas are used for the method, and

one memory area in a group of memory areas is respectively used to receive, process and transfer data in each interval of time.

12. Method according to claim 9, wherein the method is used for image processing.

13. Method according to claim 9, wherein data from a first data processing system are processed in a second data processing system, a data block to be processed

being written to a memory area of the second data processing system in a first interval of time,

being processed in the same memory area of the second data processing system in a second interval of time, and

being returned to the first data processing system from this memory area of the second data processing system in a third interval of time.

14. Method according to claim 13, wherein the second data processing system is a subsystem of the first data processing system.

15. Method according to claim 13, wherein the first data processing system is a central processing unit and the second data processing system is a coprocessor.

16. Method according to claim 13, wherein the first data processing system is a PowerPC processor element and the second data processing system is a synergistic processor element.