SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

• US 20100123170A1
• Filed: 11/18/2009
• Published: 05/20/2010
• Est. Priority Date: 11/19/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: FUJIMOTO, Hiroyuki
• Granted Patent: US 8,110,872 B2
• Time in Patent Office: Days
• US Class Current: 257/208
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A semiconductor device includes a transistor, a conductive pad, and a contact. The conductive pad is electrically connected to the transistor. The conductive pad may include, but is not limited to, a first region and a second region. The contact is electrically connected to the conductive pad. At least a main part of the first region overlaps the transistor in plan view. At least a main part of the second region does not overlap the transistor in plan view. At least a main part of the contact overlaps the second region in plan view. The at least main part of the contact does not overlap the first region in plan view. The at least main part of the contact does not overlap the transistor in plan view.

Claims

1. A semiconductor device comprising:

a transistor;

a conductive pad being electrically connected to the transistor, the conductive pad comprising a first region and a second region; and

a contact being electrically connected to the conductive pad,

wherein at least a main part of the first region overlaps the transistor in plan view,

at least a main part of the second region does not overlaps the transistor in plan view,

at least a main part of the contact overlaps the second region in plan view,

the at least main part of the contact does not overlap the first region in plan view, and

the at least main part of the contact does not overlap the transistor in plan view.

2. The semiconductor device according to claim 1, wherein the transistor comprises:

a lower diffusion layer;

a pillar disposed over the lower diffusion layer;

an upper diffusion layer disposed over the pillar, the upper diffusion layer being connected to the first region of the conductive pad.

3. The semiconductor device according to claim 1, further comprising:

a pad contact layer disposed between the upper diffusion layer and the first region of the conductive pad,

wherein the pad contact layer overlaps the upper diffusion layer and the first region of the conductive pad in plan view, and

the pad contact layer reduces a contact resistance between the upper diffusion layer and the first region of the conductive pad.

4. The semiconductor device according to claim 1, further comprising:

a capacitor disposed over the contact, the capacitor being electrically connected to the contact.

5. The semiconductor device according to claim 1, wherein plural sets of the transistor, the conductive pad and the contact are provided,

the transistors are disposed in a form of a matrix array, and

pairs of the conductive pads and the contacts are disposed in a form of a staggered array.

6. The semiconductor device according to claim 1, wherein plural sets of the transistor, the conductive pad and the contact are disposed in a form of a matrix array.

7. The semiconductor device according to claim 1, further comprising:

a metal layer disposed between the contact and the second region of the conductive pad,

wherein the conductive pad comprises a silicide layer.

8. A method of forming a semiconductor device, the method comprising:

forming a transistor;

forming a conductive pad comprising a first region and a second region, the conductive pad being electrically connected to the transistor, at least a main part of the first region overlapping the transistor in plan view, at least a main part of the second region not overlapping the transistor in plan view;

reducing a resistance of the conductive pad; and

forming a contact, at least a main part of the contact overlapping the second region in plan view, the at least main part of the contact not overlapping the first region in plan view, and the at least main part of the contact not overlapping the first region in plan view.

9. The method according to claim 8, wherein reducing the resistance of the conductive pad comprises:

introducing a dopant into a selected part of the conductive pad, at least a main part of the selected part not overlapping the transistor in plan view.

10. The method according to claim 9, wherein reducing the resistance of the conductive pad further comprises:

diffusing the dopant from the selected part to the conductive pad entirely.

11. The method according to claim 10, wherein forming the transistor comprises:

forming a lower diffusion layer;

forming a pillar over the lower diffusion layer;

forming an upper diffusion layer over the pillar, and

wherein the contact is eclectically connected to the upper diffusion layer.

12. The method according to claim 10, wherein forming the transistor comprises:

forming a lower diffusion layer;

forming a pillar over the lower diffusion layer;

forming an upper diffusion layer over the pillar, and

wherein reducing the resistance of the conductive pad is carried out using the mask having the contact hole, the mask covers the conductive pad, at least a main part of the contact hole does not overlap the first region in plan view;

13. The method according to claim 8, wherein reducing the resistance of the conductive pad is carried out using the mask having the contact hole, the mask covers the conductive pad, at least a main part of the contact hole does not overlap the first region in plan view,

reducing the resistance of the conductive pad further comprises:

forming a pad contact layer disposed between the upper diffusion layer and the first region of the conductive pad,

wherein the pad contact layer overlaps the upper diffusion layer and the first region of the conductive pad in plan view, and the pad contact layer reduces a contact resistance between the upper diffusion layer and the first region of the conductive pad.

14. The method according to claim 8, wherein reducing the resistance of the conductive pad comprises:

forming an inter-layer insulator with a contact hole over the conductive pad, the inter-layer insulator covering the conductive pad, at least a main part of the contact hole not overlapping the first region in plan view,

wherein forming the contact comprises filling a conductive material in the contact hole.

15. The method according to claim 8, wherein reducing the resistance of the conductive pad comprises:

forming a mask with a contact hole, the mask covering the conductive pad;

introducing a dopant through the contact hole into a selected part of the conductive pad, at least a main part of the selected part not overlapping the transistor in plan view; and

diffusing the dopant from the selected part to the conductive pad entirely.

16. The method according to claim 15, wherein reducing the resistance of the conductive pad further comprises:

causing a silicidation of the conductive pad after diffusing the dopant.

17. A method of forming a semiconductor device, the method comprising:

forming a transistor;

forming a conductive pad comprising a first region and a second region, the conductive pad being electrically connected to the transistor, at least a main part of the first region overlapping the transistor in plan view, at least a main part of the second region not overlapping the transistor in plan view;

forming a mask with a contact hole, the mask covering the conductive pad;

introducing a dopant through the contact hole into a selected part of the conductive pad, at least a main part of the selected part not overlapping the transistor in plan view;

diffusing the dopant from the selected part to the conductive pad entirely;

forming a contact, at least a main part of the contact overlapping the second region in plan view, the at least main part of the contact not overlapping the first region in plan view, and the at least main part of the contact does not overlap the first region in plan view.

18. The method according to claim 17, wherein forming the transistor comprises:

forming a lower diffusion layer;

forming a pillar over the lower diffusion layer; and

forming an upper diffusion layer over the pillar.

19. The method according to claim 17, wherein forming the contact comprises filling a conductive material in the contact hole.

20. The method according to claim 17, wherein reducing the resistance of the conductive pad further comprises:

causing a silicidation of the conductive pad after diffusing the dopant.