SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device, comprising:
- a TC unit series-type ferroelectric random access memory (FeRAM) comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor being connected each other in parallel, comprising;
a first electrode over and electrically connected to one of a source and a drain in the memory transistor;
a second electrode opposite to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor;
a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode; and
a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode;
wherein the ferroelectric capacitor comprises the first electrode, the third electrode and the ferroelectric film.
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Accused Products
Abstract
According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film.
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Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a TC unit series-type ferroelectric random access memory (FeRAM) comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor being connected each other in parallel, comprising; a first electrode over and electrically connected to one of a source and a drain in the memory transistor; a second electrode opposite to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor; a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode; and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode; wherein the ferroelectric capacitor comprises the first electrode, the third electrode and the ferroelectric film. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory device, comprising:
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a TC unit series type FeRAM comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor being connected each other in parallel, comprising; a first electrode over and electrically connected to one of a source and a drain in the memory transistor; a ferroelectric film on at least both sidewalls of the first electrode along a bit line direction; a second electrode opposite to the first electrode over and electrically connected the other of the source and the drain in the memory transistor, and in a contact opening in the ferroelectric film; wherein the ferroelectric capacitor comprises the first electrode, the second electrode, the ferroelectric film and the contact opening located one pitch to the bit line direction in the adjacent memory cells. - View Dependent Claims (13, 14, 15)
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16. A method for fabricating a semiconductor memory device, comprising:
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fabricating a TC unit series type FeRAM comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, comprising; forming the memory transistor over a semiconductor substrate, the memory transistor being surrounded by an element isolation region, the memory transistor comprising a channel region between a source and a drain, and a gate insulator and a gate electrode film in layer on the channel region; forming a first inter-layer insulator on the memory transistor; selectively removing the first inter-layer insulator in order to form a first opening on the source and the drain; embedding a first conductive film in the first opening in order to form a plug, the plug configured to connect to the source and the drain; forming a second inter-layer insulator on the first inter-layer insulator and the plug; selectively removing the second inter-layer insulator in order to form a second opening on the plug; embedding a second conductive film in the second opening in order to form a via electrode; forming a first diffusion barrier film on the second inter-layer insulator and the via electrode; forming a third inter-layer insulator on the first diffusion barrier film; selectively removing the third inter-layer insulator and the first diffusion barrier film in order to form a third opening on the via electrode over one of the source and the drain; embedding a third conductive film in the third opening in order to form a first electrode; selectively removing the third inter-layer insulator and the first electrode in order to expose a surface of the first diffusion barrier film; selectively removing the first electrode and the first diffusion barrier film in order to form a fourth opening on the via electrode over the other of the source and the drain; forming a ferroelectric film over the semiconductor substrate; forming a second electrode on the ferroelectric film; selectively removing the second electrode in order to leave a sidewall of the second electrode; forming a fifth opening on the via electrode over the other of the source and the drain in the transistor; and embedding a fourth conductive film in the fifth opening in order to form a third electrode. - View Dependent Claims (17, 18, 19, 20)
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Specification