SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE

• US 20100123177A1
• Filed: 11/17/2009
• Published: 05/20/2010
• Est. Priority Date: 11/17/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OZAKI, Tohru
• Application Number:
  US12/620,424
• Publication Number:
  US 20100123177A1
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H10B 53/10 characterised by the top-view layout
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film.

Claims

1. A semiconductor memory device, comprising:

a TC unit series-type ferroelectric random access memory (FeRAM) comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor being connected each other in parallel, comprising;

a first electrode over and electrically connected to one of a source and a drain in the memory transistor;

a second electrode opposite to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor;

a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode; and

a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode;

wherein the ferroelectric capacitor comprises the first electrode, the third electrode and the ferroelectric film.

2. The semiconductor memory device of claim 1, further comprising:

pedestal electrodes on a bottom surface of the first electrode and a bottom surface of the second electrode.

3. The semiconductor memory device of claim 1, further comprising:

a dielectric film on both sidewalls of the first electrode along a word line direction, permittivity of the dielectric film being lower than permittivity of the ferroelectric film, the dielectric film configured to prevent materials in the ferroelectric film from diffusing to an outer region.

4. The semiconductor memory device of claim 1, wherein

a size in the word line direction of the first electrode is larger than a size in a bit line direction of the first electrode and a size in the bit line direction of the second electrode is larger than a size in the word line direction of the second electrode.

5. The semiconductor memory device of claim 1, further comprising:

a diffusion barrier layer on upper surfaces of the first electrode, the second electrode, the third electrode and the ferroelectric film, the diffusion barrier layer configured to prevent materials in the ferroelectric film from diffusing to the outer region.

6. The semiconductor memory device of claim 1, wherein

the first electrode comprises one of iridium (Ir), ruthenium (Ru), strontium ruthenium oxide (SrRuO_X) and ruthenium oxide (RuO_X).

7. The semiconductor memory device of claim 1, wherein

the second electrode comprises one of Ir, iridium oxide (IrO_X), SrRuO_X and RuO_X.

8. The semiconductor memory device of claim 1, wherein

the third electrode comprises one of Ir, IrO_X, SrRuO_X, RuO_X and IrO_X and Ir laterally in layer in an order or IrOx, Ir, and IrOx.

9. The semiconductor memory device of claim 1, wherein

the diffusion barrier layer is aluminum oxide (Al₂O₃) or silicon nitride film (Si₃N₄).

10. The semiconductor memory device of claim 2, wherein

each pedestal electrode comprises a stacked structure comprising either titanium aluminum nitride (TiAlN) and Ir or titanium nitride iridium (TiNIr) and Ir.

11. The semiconductor memory device of claim 2, wherein

the ferroelectric film comprises one of lead zirconate titanate (PZT), SrBi₂Ta₂O₉ (SBT), (Bi,La)₄Ti₃O₁₂ (BLT), or BaTi₂O₅.

12. A semiconductor memory device, comprising:

a TC unit series type FeRAM comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor being connected each other in parallel, comprising;

a first electrode over and electrically connected to one of a source and a drain in the memory transistor;

a ferroelectric film on at least both sidewalls of the first electrode along a bit line direction;

a second electrode opposite to the first electrode over and electrically connected the other of the source and the drain in the memory transistor, and in a contact opening in the ferroelectric film;

wherein the ferroelectric capacitor comprises the first electrode, the second electrode, the ferroelectric film and the contact opening located one pitch to the bit line direction in the adjacent memory cells.

13. The semiconductor memory device of claim 12, further comprising:

a third electrode between the contact opening and the ferroelectric film, the contact opening being opened via the third electrode.

14. The semiconductor memory device of claim 12, further comprising:

pedestal electrodes on a bottom surface of the first electrode and a bottom surface of the second electrode.

15. The semiconductor memory device of claim 12, further comprising:

a dielectric film on both sidewalls of the first electrode along a word line direction, permittivity of the dielectric film being lower than permittivity of the ferroelectric film, the dielectric film configured to prevent materials in the ferroelectric film from diffusing to an outer region.

16. A method for fabricating a semiconductor memory device, comprising:

fabricating a TC unit series type FeRAM comprising a plurality of memory cells serially connected, each memory cell comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, comprising;

forming the memory transistor over a semiconductor substrate, the memory transistor being surrounded by an element isolation region, the memory transistor comprising a channel region between a source and a drain, and a gate insulator and a gate electrode film in layer on the channel region;

forming a first inter-layer insulator on the memory transistor;

selectively removing the first inter-layer insulator in order to form a first opening on the source and the drain;

embedding a first conductive film in the first opening in order to form a plug, the plug configured to connect to the source and the drain;

forming a second inter-layer insulator on the first inter-layer insulator and the plug;

selectively removing the second inter-layer insulator in order to form a second opening on the plug;

embedding a second conductive film in the second opening in order to form a via electrode;

forming a first diffusion barrier film on the second inter-layer insulator and the via electrode;

forming a third inter-layer insulator on the first diffusion barrier film;

selectively removing the third inter-layer insulator and the first diffusion barrier film in order to form a third opening on the via electrode over one of the source and the drain;

embedding a third conductive film in the third opening in order to form a first electrode;

selectively removing the third inter-layer insulator and the first electrode in order to expose a surface of the first diffusion barrier film;

selectively removing the first electrode and the first diffusion barrier film in order to form a fourth opening on the via electrode over the other of the source and the drain;

forming a ferroelectric film over the semiconductor substrate;

forming a second electrode on the ferroelectric film;

selectively removing the second electrode in order to leave a sidewall of the second electrode;

forming a fifth opening on the via electrode over the other of the source and the drain in the transistor; and

embedding a fourth conductive film in the fifth opening in order to form a third electrode.

17. The method for fabricating the semiconductor memory device of claim 16, further comprising;

forming a fourth inter-layer insulator on the first inter-layer insulator and the via electrode after forming the via electrode and before forming the first diffusion barrier film;

selectively removing the fourth inter-layer insulator in order to form a fifth opening on the via electrode after forming the via electrode and before forming the first diffusion barrier film; and

embedding a fifth conductive film on the fifth opening in order to form a fourth electrode, the fourth electrode connecting between the via electrode and the first electrode, after forming the via electrode and before forming the first diffusion barrier film.

18. The method for fabricating the semiconductor memory device of claim 16, wherein

the first diffusion barrier film is left on a sidewall of the first electrode along a word line direction in the selectively removing the first electrode and the first diffusion barrier film.

19. The method for fabricating the semiconductor memory device of claim 16, wherein

a size in the word line direction of the first electrode is larger than a size in a bit line direction of the first electrode and a size in the bit line direction of the second electrode is larger than a size in the word line direction of the second electrode.

20. The method for fabricating the semiconductor memory device of claim 16, further comprising;

forming a second diffusion barrier film on the third electrode, the ferroelectric film, the second electrode after the forming the third electrode.