SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

• US 20100123193A1
• Filed: 11/14/2008
• Published: 05/20/2010
• Est. Priority Date: 11/14/2008
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Barber, Duane B., Pratt, Brian, Burke, Peter A.
• Application Number:
  US12/271,092
• Publication Number:
  US 20100123193A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second major surfaces;

forming a plurality of trenches in the semiconductor material, wherein a first trench of the plurality of trenches has at least one sidewall;

forming a first layer of dielectric material over the plurality of trenches;

forming a first layer of polysilicon in a first portion of a first trench of the plurality of trenches;

planarizing the first layer of polysilicon to form a first polysilicon electrode in the first portion of a first trench of the plurality of trenches, the first polysilicon electrode having opposing sides;

recessing the first polysilicon electrode;

forming a second layer of dielectric material over the first polysilicon electrode that has been recessed;

forming a second layer of polysilicon over the second layer of dielectric material and over first polysilicon electrode that has been recessed; and

planarizing the second layer of polysilicon to form a second polysilicon electrode over the first polysilicon electrode that has been recessed, wherein polysilicon is substantially absent over the first major surface.

2. The method of claim 1, wherein planarizing the second layer of polysilicon removes the second layer of polysilicon over the first major surface.

3. The method of claim 1, wherein recessing the first polysilicon electrode comprises isotropically etching the first polysilicon electrode.

4. The method of claim 3, wherein planarizing the first layer of polysilicon and planarizing the second layer of polysilicon comprises using a chemical mechanical planarization process to planarize the first and second layers of polysilicon.

5. The method of claim 3, wherein forming the plurality of trenches comprises forming a second trench in the semiconductor material, the second trench having at least one sidewall, and wherein forming the first layer of dielectric material includes forming the first layer of dielectric material over the at least one sidewall of the second trench, and further including:

forming the first layer of polysilicon in a first portion of the second trench;

planarizing the first layer of polysilicon to form a third polysilicon electrode, the third polysilicon electrode in the first portion of the second trench and having opposing sides;

recessing the third polysilicon electrode;

forming the second layer of dielectric material over the third polysilicon electrode that has been recessed;

forming the second layer of polysilicon over the second layer of dielectric material and over the third polysilicon electrode that has been recessed; and

planarizing the second layer of polysilicon to form a fourth polysilicon electrode over the third polysilicon electrode that has been recessed, wherein polysilicon is substantially absent over the first major surface.

6. The method of claim 5, further including forming a first doped region of a first conductivity type between the first and second trenches.

7. The method of claim 6, further including forming a second doped region of a second conductivity type, the second doped region within the first doped region.

8. The method of claim 5, wherein forming the plurality of trenches comprises forming a third trench in the semiconductor material, the third trench having at least one sidewall, and wherein forming the first layer of dielectric material includes forming the first layer of dielectric material over the at least one sidewall of the third trench, and further including:

forming the first layer of polysilicon in a first portion of the third trench;

planarizing the first layer of polysilicon to form a fifth polysilicon electrode, the fifth polysilicon electrode in the first portion of the third trench and having opposing sides;

recessing the fifth polysilicon electrode;

forming the second layer of dielectric material over the fifth polysilicon electrode that has been recessed;

forming the second layer of polysilicon over the second layer of dielectric material and over the fifth polysilicon electrode that has been recessed; and

planarizing the second layer of polysilicon to form a sixth polysilicon electrode over the fifth polysilicon electrode that has been recessed, wherein polysilicon is substantially absent over the first major surface.

9. The method of claim 8, wherein forming the plurality of trenches comprises forming a fourth trench in the semiconductor material and further including forming a seventh polysilicon electrode in the fourth trench.

10. The method of claim 9, further including recessing the seventh polysilicon electrode.

11. The method of claim 10, further including electrically connecting the first, third, and fifth polysilicon electrodes.

12. The method of claim 10, further including forming cobalt silicide from the portions of the second, fourth, and sixth polysilicon electrodes.

13. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material of a first conductivity type having first and second surfaces;

forming a plurality of trenches in the semiconductor material, each trench of the plurality of trenches having a floor and sidewalls;

forming a first layer of dielectric material over at least the floors and sidewalls of the plurality of trenches;

forming a first layer of polysilicon over the first layer of dielectric material;

planarizing the first layer of polysilicon;

removing a first portion of the first layer of polysilicon that is in at least a first trench of the plurality of trenches;

forming a second layer of dielectric material in the first trench;

forming a second layer of polysilicon over the second layer of dielectric material; and

planarizing the second layer of polysilicon, wherein a portion of the second layer of polysilicon remains in at least the first trench and wherein polysilicon from at least the second layer of polysilicon is absent over the first surface.

14. The method of claim 13, wherein the second layer of dielectric material is a gate oxide.

15. The method of claim 13, wherein removing the first portion of the first layer of polysilicon includes:

removing portions of the first layer of polysilicon that are in second and third trenches of the plurality of trenches; and

wherein

forming the second layer of dielectric material includes forming the second layer of dielectric material in the second and third trenches; and

wherein

planarizing the second layer of polysilicon includes leaving portions of the second layer of polysilicon in the second and third trenches.

16. The method of claim 15, wherein forming the plurality of trenches includes forming a fourth trench, wherein forming the first layer of polysilicon includes forming the first layer of polysilicon in the fourth trench, and wherein planarizing the first layer of polysilicon includes leaving a portion of the first layer of polysilicon in the fourth trench.

17. The method of claim 16, further including:

forming a first doped region of a second conductivity type in a portion of the semiconductor material that is between the first and second trenches; and

forming a second doped region of the first conductivity type in a portion of the first doped region.

18. A semiconductor component, comprising:

a semiconductor material of a first conductivity type and having first and second major surfaces;

a plurality of trenches in the semiconductor material, wherein first and second trenches of the plurality of trenches extend from the first major surface into the semiconductor material, and wherein the first and second trenches have floors and sidewalls;

a first layer of dielectric material on the floors and sidewalls of the first and second trenches;

first and second shielding electrodes on the first layer of dielectric material in the first and second trenches, respectively;

a second layer of dielectric material on the first and second shielding electrodes;

a gate oxide on the second layer of dielectric material and on the sidewalls of the first and second trenches;

first and second polysilicon gate electrodes on the gate oxide in the first and second trenches, respectively, wherein polysilicon is absent above the first major surface;

a first doped region of a second conductivity type extending into a portion of the semiconductor material that is between the first and second trenches; and

a second doped region of the first conductivity type extending into a portion of the first doped region.

19. The semiconductor component of claim 18, wherein the plurality of trenches further includes third and fourth trenches in the semiconductor material, and further including:

the first layer of dielectric material on the floors and sidewalls of the third and fourth trenches;

third and fourth shielding electrodes on the first layer of dielectric material in the third and fourth trenches, respectively;

the second layer of dielectric material on the third shielding electrode;

the gate oxide on the second layer of dielectric material and on the sidewalls of the first and second trenches; and

a third polysilicon gate electrode on the gate oxide in the third trench.

20. The semiconductor component of claim 18, wherein the first and second shielding electrodes are electrically connected to each other and the first and second polysilicon gate electrodes are electrically connected to each other.