INTEGRATED CIRCUIT WITH STACKED DEVICES

• US 20100123202A1
• Filed: 11/14/2008
• Published: 05/20/2010
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: ChangXin Memory Technologies, Inc.
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Hofmann, Franz
• Granted Patent: US 8,241,989 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming first structures on first portions of a surface of a first semiconductor structure of a first crystalline semiconductor material;

forming sacrificial structures of a second crystalline material on second portions of the surface between the first portions, wherein the first crystalline semiconductor material is effective as a crystal seed for the second crystalline material; and

forming a second, crystalline semiconductor structure of the first crystalline semiconductor material over the sacrificial structures and over the first structures, wherein the sacrificial structures are effective as a crystal seed for the first crystalline semiconductor material.

2. The method of claim 1, comprising wherein the second crystalline material is a second crystalline semiconductor material different from the first crystalline semiconductor material.

3. The method of claim 1, comprising wherein a first lattice constant of the first crystalline semiconductor material and a second lattice constant of the second crystalline material deviate by at most 1% from each other.

4. The method of claim 1, comprising wherein the first crystalline semiconductor material is single-crystalline silicon.

5. The method of claim 4, comprising wherein the second crystalline material has a cubic diamond lattice structure.

6. The method of claim 4, comprising wherein the second crystalline material is a single-crystalline silicon germanium alloy SiGe.

7. The method of claim 4, comprising wherein the first semiconductor structure is a silicon wafer or a silicon layer arranged upon a dielectric base.

8. The method of claim 1, further comprising:

forming second structures on the second semiconductor structure.

9. The method of claim 1, further comprising:

forming source/drain regions and channel regions of field effect transistor structures in the second semiconductor structure, wherein the channel regions are formed in a vertical projection above the sacrificial structures.

10. The method of claim 1, further comprising:

forming source/drain regions and channel regions of field effect transistor structures in the second semiconductor structure, wherein the source/drain regions are formed in a vertical projection above the sacrificial structures.

11. The method of claim 1, further comprising:

removing the sacrificial structures to form voids between neighboring first structures respectively.

12. The method of claim 11, further comprising:

removing first portions of the second semiconductor structure at least partly to uncover portions of the sacrificial structures, before removing the sacrificial structures.

13. The method of claim 1, comprising wherein the first structures are gate electrodes of memory cells arranged to NAND strings.

14. A method of manufacturing an integrated circuit, comprising:

forming first gate structures arranged along a string on first portions of a surface of a first semiconductor structure of a first crystalline semiconductor material;

forming sacrificial structures of a second crystalline material on second portions of the surface between the first portions; and

forming a second semiconductor structure of the first crystalline semiconductor material on the sacrificial structures and above the first gate structures, wherein the first portions are effective as a crystal seed for the sacrificial structures and the sacrificial structures are effective as a crystal seed for the second semiconductor structure.

15. The method of claim 14, comprising wherein the first crystalline semiconductor material is single-crystalline silicon.

16. The method of claim 15, comprising wherein the second crystalline semiconductor material is a crystalline silicon germanium alloy SiGe.

17. The method of claim 14, further comprising:

forming second gate structures arranged to strings on the second semiconductor structure.

18. The method of claim 14, further comprising:

removing first portions of the second semiconductor structure to uncover portions of the sacrificial structures; and

removing the sacrificial structures at least partly to form voids between neighboring first gate structures respectively.

19. The method of claim 14, comprising forming the second gate structures in the vertical projection of the sacrificial structures.

20. A method of manufacturing an integrated circuit, the method comprising:

covering first portions of a surface of a first semiconductor carrier with a cover material, the first semiconductor carrier comprising a first crystalline semiconductor material;

forming a sacrificial crystalline material over second portions of the surface between the first portions, wherein the first crystalline semiconductor material is effective as a crystal seed; and

forming the first crystalline semiconductor material over the sacrificial crystalline material and over the first portions, wherein the sacrificial crystalline material is effective as a crystal seed.

21. An integrated circuit comprising:

a plurality of gate structures of first transistor structures arranged along a first line on a first semiconductor structure of a single-crystalline semiconductor material;

a plurality of further gate structures of second transistor structures arranged along a second line extending parallel and above in the vertical projection of the first line on a second semiconductor structure of the single-crystalline semiconductor material, wherein channel regions of the second transistor elements are formed above spaces between the gate structures of the first transistor structures.

22. The integrated circuit of claim 21, comprising wherein the gate structures and the further gate structures have the same pitch.

23. The integrated circuit of claim 21, comprising wherein the second line extends in the vertical projection of the first line.