Feature Patterning Methods and Structures Thereof

• US 20100123250A1
• Filed: 11/14/2008
• Published: 05/20/2010
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Postnikov, Sergei, Schulz, Thomas
• Granted Patent: US 7,981,789 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/027 Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 photographic masks or originals per se G03F1/00; registration or positioning of photographic masks or originals G03F9/00; photographic cameras G03B; control of position G05D3/00
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

Claims

1. A method of patterning a feature, the method comprising:

forming a first portion of the feature in a first material layer;

forming a second portion of the feature in the first material layer; and

forming a third portion of the feature in a second material layer.

2. The method according to claim 1, wherein forming the first portion of the feature comprises using a first lithography process, wherein forming the second portion of the feature comprises using a second lithography process, the second lithography process being different than the first lithography process.

3. The method according to claim 1, wherein forming the third portion comprises forming a third portion having a first end and a second end, wherein forming the third portion comprises coupling the first end of the third portion to the first portion of the feature and coupling the second end of the third portion to the second portion of the feature.

4. The method according to claim 1, wherein forming the first portion and forming the second portion comprise forming a first portion and a second portion that do not intersect or barely intersect, wherein forming the third portion comprises coupling the first portion to the second portion.

5. The method according to claim 1, wherein forming the first portion, forming the second portion, and forming the third portion comprise forming a conductive line.

6. The method according to claim 1, wherein forming the first portion, forming the second portion, or forming the third portion comprise forming a metal, a semiconductive material, or a combination or multiple layers thereof.

7. The method according to claim 1, wherein forming the first portion, forming the second portion, or forming the third portion comprise a subtractive etch process.

8. The method according to claim 1, wherein forming the first portion, forming the second portion, or forming the third portion comprise a damascene process.

9. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a first material layer and a second material layer over the workpiece, the second material layer being adjacent the first material layer;

patterning a first portion of a feature in the first material layer using a first lithography mask or process;

patterning a second portion of the feature in the first material layer using a second lithography mask or process; and

forming a third portion of the feature in the second material layer, wherein the third portion of the feature couples the first portion of the feature to the second portion of the feature.

10. The method according to claim 9, wherein forming the first material layer and the second material layer comprises first, forming the first material layer over the workpiece, and second, forming the second material layer over the first material layer, wherein the method comprises forming the first portion of the feature and forming the second portion of the feature before forming the third portion of the feature.

11. The method according to claim 9, wherein forming the first material layer and the second material layer comprises first, forming the second material layer over the workpiece, and second, forming the first material layer over the second material layer, wherein the method comprises forming the first portion of the feature and forming the second portion of the feature after forming the third portion of the feature.

12. The method according to claim 9, wherein forming the third portion comprises forming a stitching bridge of the feature.

13. The method according to claim 9, further comprising forming at least one contact or at least one via in the second material layer.

14. The method according to claim 13, wherein forming the third portion comprises forming a third portion that is substantially the same size or larger than the at least one contact or the at least one via.

15. The method according to claim 13, wherein forming the third portion and forming the at least one contact or the at least one via comprise simultaneously forming the third portion and the at least one contact or the at least one via in the second material layer.

16. The method according to claim 13, wherein forming the at least one contact or the at least one via comprises coupling the first portion or the second portion of the feature to an active area of the workpiece or to conductive lines of the semiconductor device.

17. The method according to claim 16, wherein coupling the first portion of the second portion of the feature to the active area of the workpiece comprises coupling the first portion or the second portion of the feature to a gate contact, a source, or a drain of a transistor.

18. A semiconductor device, comprising:

a workpiece;

a first material layer and a second material layer disposed over the workpiece, the second material layer being adjacent the first material layer;

a first portion of a feature being disposed in the first material layer;

a second portion of the feature being disposed in the first material layer; and

a third portion of the feature being disposed in the second material layer, wherein the third portion of the feature couples the first portion of the feature to the second portion of the feature.

19. The semiconductor device according to claim 18, wherein the first material layer comprises a conductive line layer of the semiconductor device.

20. The semiconductor device according to claim 18, wherein the second material layer comprises a contact layer or a via layer of the semiconductor device.

21. The semiconductor device according to claim 18, wherein end regions of the third portion of the feature are disposed over end regions of the first portion of the feature and the second portion of the feature, or wherein end regions of the first portion of the feature and end regions of the second portion of the feature are disposed over end regions of the third portion of the feature.